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A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.131-140

2012

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A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.191-203

2015

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A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

2011 IEEE International Solid-State Circuits Conference, 2011, p.502-504

2011

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Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

2009 IEEE Custom Integrated Circuits Conference, 2009, p.717-720

2009

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A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.3861-3864

2010

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A single-loop DLL using an OR-AND duty-cycle correction technique

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.245-248

2008

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A low power and high performance robust digital delay locked loop against noisy environments

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.241-244

2008

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An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, p.1-2

2014

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A wide-range all-digital multiphase DLL with supply noise tolerance

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.421-424

2008

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25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.432-433

2014

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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.282-613

2008

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A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.184-595

2007

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A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.401-404

2005

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A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

2006 IEEE Asian Solid-State Circuits Conference, 2006, p.323-326

2006

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Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.280-613

2008

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A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.140-141,141a

2009

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A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.547-556

2006

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A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 2003, p.283-284

2003

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A Wireless Pressure Sensor Integrated with a Biodegradable Polymer Stent for Biomedical Applications

Sensors (Basel, Switzerland), 2016-06, Vol.16 (6), p.809-809

2016

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Intranasal immunization with the recombinant measles virus encoding the spike protein of SARS-CoV-2 confers protective immunity against COVID-19 in hamsters

Vaccine, 2024-01, Vol.42 (2), p.69-74

2024

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Biodegradable polymer material based smart stent: Wireless pressure sensor and 3D printed stent

Microelectronic engineering, 2019-02, Vol.206, p.1-5

2019

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Wireless pressure sensor integrated with a 3D printed polymer stent for smart health monitoring

Sensors and actuators. B, Chemical, 2019-02, Vol.280, p.201-209

2019

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Wild boar harbouring African swine fever virus in the demilitarized zone in South Korea, 2019

Emerging microbes & infections, 2020-01, Vol.9 (1), p.628-630

2020

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Efficacy and Safety of Sorafenib Therapy on Metastatic Renal Cell Carcinoma in Korean Patients: Results from a Retrospective Multicenter Study

PloS one, 2015-08, Vol.10 (8), p.e0135165-e0135165

2015

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Preoperative Identification of a Low-Risk Group for Lymph Node Metastasis in Endometrial Cancer: A Korean Gynecologic Oncology Group Study

Journal of clinical oncology, 2012-04, Vol.30 (12), p.1329-1334

2012

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A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

A single-loop DLL using an OR-AND duty-cycle correction technique

A low power and high performance robust digital delay locked loop against noisy environments

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

A wide-range all-digital multiphase DLL with supply noise tolerance

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM

A Wireless Pressure Sensor Integrated with a Biodegradable Polymer Stent for Biomedical Applications

Intranasal immunization with the recombinant measles virus encoding the spike protein of SARS-CoV-2 confers protective immunity against COVID-19 in hamsters

Biodegradable polymer material based smart stent: Wireless pressure sensor and 3D printed stent

Wireless pressure sensor integrated with a 3D printed polymer stent for smart health monitoring

Wild boar harbouring African swine fever virus in the demilitarized zone in South Korea, 2019

Efficacy and Safety of Sorafenib Therapy on Metastatic Renal Cell Carcinoma in Korean Patients: Results from a Retrospective Multicenter Study

Preoperative Identification of a Low-Risk Group for Lymph Node Metastasis in Endometrial Cancer: A Korean Gynecologic Oncology Group Study

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