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Corrigendum to “Phase-leg power equalization method of modular multilevel converter with APOD strategy under unbalanced fault condition” [Int. J. Electr. Power Energy Syst. 153 (2023) 109176]

International journal of electrical power & energy systems, 2024-07, Vol.158, p.109780, Article 109780

2024

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Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

IEEE access, 2021, Vol.9, p.57393-57403

2021

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Implementation of three-phase four-leg inverter using SiC MOSFET for UPS applications

Journal of Power Electronics, 2021, 21(1), , pp.103-112

2021

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Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC

IEEE access, 2020, Vol.8, p.216922-216932

2020

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Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution

IEEE transactions on circuits and systems. II, Express briefs, 2016-10, Vol.63 (10), p.964-968

2016

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Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

IEEE transactions on very large scale integration (VLSI) systems, 2016-04, Vol.24 (4), p.1342-1350

2016

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Analyzing and Designing a Current Controller for Circulating Current Reduction in Parallel Three-Phase Voltage-Source Inverters

JOURNAL OF POWER ELECTRONICS, 2018-03, Vol.18 (2), p.502-510

2018

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Application of Pulsed Green Laser Activation to Top-Tier MOSFET Fabrication for Monolithic 3-D Integration

IEEE transactions on electron devices, 2024-01, Vol.71 (1), p.890-895

2024

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An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s

IEEE journal of solid-state circuits, 2023-11, Vol.58 (11), p.1-11

2023

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A Seamless Transfer Algorithm Based on Frequency Detection with Feedforward Control Method in Distributed Generation System

JOURNAL OF POWER ELECTRONICS, 2015-07, Vol.15 (4), p.1066-1073

2015

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A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC

IEEE journal of solid-state circuits, 2022-06, Vol.57 (6), p.1913-1923

2022

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0.293-mm 2 Fast Transient Response Hysteretic Quasi- $V^{2}$ DC–DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35- $\mu$ m CMOS

IEEE journal of solid-state circuits, 2018-06, Vol.53 (6), p.1844-1855

2018

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0.293-mm2 Fast Transient Response Hysteretic Quasi- V^ DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35- \mu m CMOS

IEEE journal of solid-state circuits, 2018-06, Vol.53 (6), p.1844-1855

2018

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A 0.166 pJ/b/pF, 3.5–5 Gb/s TSV I/O Interface With V OH Drift Control

IEEE transactions on circuits and systems. II, Express briefs, 2021-06, Vol.68 (6), p.1822-1826

2021

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0.293-mm2 Fast Transient Response Hysteretic Quasi-[Formula Omitted] DC–DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-[Formula Omitted]m CMOS

IEEE journal of solid-state circuits, 2018-01, Vol.53 (6), p.1844

2018

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SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.1567-1571

2022

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Phase-leg power equalization method of modular multilevel converter with APOD strategy under unbalanced fault condition

International journal of electrical power & energy systems, 2023-11, Vol.153, p.109176, Article 109176

2023

Volltextzugriff (PDF)

A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges

IEEE transactions on circuits and systems. II, Express briefs, 2021-04, Vol.68 (4), p.1433-1437

2021

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Ultralow- \textit Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

IEEE transactions on electron devices, 2023-03, p.1-6

2023

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An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference

IEEE transactions on circuits and systems. II, Express briefs, 2023-09, Vol.70 (9), p.3243-3247

2023

Volltextzugriff (PDF)

A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With VOH Drift Control

IEEE transactions on circuits and systems. II, Express briefs, 2021-06, Vol.68 (6), p.1822-1826

2021

Volltextzugriff (PDF)

A 6.9-μm 2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges

IEEE transactions on circuits and systems. II, Express briefs, 2021-04, Vol.68 (4), p.1433-1437

2021

Volltextzugriff (PDF)

Ultralow- k Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

IEEE transactions on electron devices, 2023-05, Vol.70 (5), p.2588-2593

2023

Volltextzugriff (PDF)

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling

IEEE journal of solid-state circuits, 2022-04, Vol.57 (4), p.1039-1048

2022

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The age of the Paleolithic handaxes from the Imjin–Hantan River Basins, South Korea

Quaternary international, 2012-12, Vol.281, p.14-25

2012

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Corrigendum to “Phase-leg power equalization method of modular multilevel converter with APOD strategy under unbalanced fault condition” [Int. J. Electr. Power Energy Syst. 153 (2023) 109176]

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

Implementation of three-phase four-leg inverter using SiC MOSFET for UPS applications

Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC

Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Analyzing and Designing a Current Controller for Circulating Current Reduction in Parallel Three-Phase Voltage-Source Inverters

Application of Pulsed Green Laser Activation to Top-Tier MOSFET Fabrication for Monolithic 3-D Integration

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s

A Seamless Transfer Algorithm Based on Frequency Detection with Feedforward Control Method in Distributed Generation System

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC

0.293-mm 2 Fast Transient Response Hysteretic Quasi- $V^{2}$ DC–DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35- $\mu$ m CMOS

0.293-mm2 Fast Transient Response Hysteretic Quasi- V^ DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35- \mu m CMOS

A 0.166 pJ/b/pF, 3.5–5 Gb/s TSV I/O Interface With V OH Drift Control

0.293-mm2 Fast Transient Response Hysteretic Quasi-[Formula Omitted] DC–DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-[Formula Omitted]m CMOS

SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation

Phase-leg power equalization method of modular multilevel converter with APOD strategy under unbalanced fault condition

A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges

Ultralow- \textit Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference

A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With VOH Drift Control

A 6.9-μm 2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges

Ultralow- k Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling

The age of the Paleolithic handaxes from the Imjin–Hantan River Basins, South Korea

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