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Analysis on New Read Disturbance Induced by Hot Carrier Injections in 3-D Channel-Stacked NAND Flash Memory

IEEE transactions on electron devices, 2019-08, Vol.66 (8), p.3326-3330

2019

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Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

IEEE transactions on electron devices, 2016-03, Vol.63 (3), p.1041-1046

2016

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Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

IEEE transactions on electron devices, 2016-09, Vol.63 (9), p.3521-3526

2016

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Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

IEEE electron device letters, 2016-11, Vol.37 (11), p.1418-1421

2016

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Effect of Ferronickel Slag Powder on Microhydration Heat, Flow, Compressive Strength, and Drying Shrinkage of Mortar

Advances in Civil Engineering, 2018-01, Vol.2018 (2018), p.1-7

2018

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Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

IEEE electron device letters, 2015-12, Vol.36 (12), p.1318-1320

2015

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Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(2), 74, pp.260-264

2017

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13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.236-237

2024

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Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

Solid-state electronics, 2018-02, Vol.140, p.46-50

2018

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A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory

2013 IEEE 5th International Nanoelectronics Conference (INEC), 2013, p.69-71

2013

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Effects of nitride trap layer properties on location of charge centroid in charge-trap flash memory

2017 Silicon Nanoelectronics Workshop (SNW), 2017, p.79-80

2017

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A boosted common source line program scheme in channel stacked NAND flash memory with layer selection by multilevel operation

2017 Silicon Nanoelectronics Workshop (SNW), 2017, p.77-78

2017

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Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Japanese Journal of Applied Physics, 2012-07, Vol.51 (7R), p.74301

2012

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Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory

International journal of nanotechnology., 2014, Vol.11 (1/2/3/4), p.116

2014

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Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

Journal of semiconductor technology and science, 2017, Vol.17 (2), p.260-264

2017

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Threshold Voltage Setting Method for Layer Selection by Multi-Level Operation in Channel Stacked NAND Flash Memory

Journal of nanoscience and nanotechnology, 2017-05, Vol.17 (5), p.3386-3389

2017

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Interface and oxide trap analysis at tunnel oxide of NAND flash memory with excluding the effect of floating gate

2016 IEEE Silicon Nanoelectronics Workshop (SNW), 2016, p.90-91

2016

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Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Japanese Journal of Applied Physics, 2012-07, Vol.51 (7), p.074301-074301-6

2012

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Investigation of self boosting disturbance induced by channel coupling in 3D stacked NAND flash memory

2011 International Semiconductor Device Research Symposium (ISDRS), 2011, p.1-2

2011

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Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

2012 IEEE Silicon Nanoelectronics Workshop (SNW), 2012, p.1-2

2012

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Outage Analysis of User Pairing Algorithm for Full-Duplex Cellular Networks

Wireless communications and mobile computing, 2019-01, Vol.2019 (2019), p.1-12

2019

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A fouling mitigation device for a wastewater heat recovery heat pump system using a bubbling fluidized bed with cleaning sponge balls

Journal of the Korean Society of Marine Engineering, 2016-03, Vol.40 (3), p.152-156

2016

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Unguided de-escalation from ticagrelor to clopidogrel in stabilised patients with acute myocardial infarction undergoing percutaneous coronary intervention (TALOS-AMI): an investigator-initiated, open-label, multicentre, non-inferiority, randomised trial

The Lancet (British edition), 2021-10, Vol.398 (10308), p.1305-1316

2021

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Different clinical characteristics and impact of carbapenem-resistance on outcomes between Acinetobacter baumannii and Pseudomonas aeruginosa bacteraemia: a prospective observational study

Scientific reports, 2022-05, Vol.12 (1), p.8527-8527, Article 8527

2022

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Effect of mode and schedule of administration on carcinogenic effect of N-methyl-N?-nitro-N-nitrosoguanidine in rats

Bulletin of experimental biology and medicine, 1990-02, Vol.109 (2), p.217-218

1990

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Analysis on New Read Disturbance Induced by Hot Carrier Injections in 3-D Channel-Stacked NAND Flash Memory

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

Effect of Ferronickel Slag Powder on Microhydration Heat, Flow, Compressive Strength, and Drying Shrinkage of Mortar

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory

Effects of nitride trap layer properties on location of charge centroid in charge-trap flash memory

A boosted common source line program scheme in channel stacked NAND flash memory with layer selection by multilevel operation

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory

Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

Threshold Voltage Setting Method for Layer Selection by Multi-Level Operation in Channel Stacked NAND Flash Memory

Interface and oxide trap analysis at tunnel oxide of NAND flash memory with excluding the effect of floating gate

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

Investigation of self boosting disturbance induced by channel coupling in 3D stacked NAND flash memory

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

Outage Analysis of User Pairing Algorithm for Full-Duplex Cellular Networks

A fouling mitigation device for a wastewater heat recovery heat pump system using a bubbling fluidized bed with cleaning sponge balls

Unguided de-escalation from ticagrelor to clopidogrel in stabilised patients with acute myocardial infarction undergoing percutaneous coronary intervention (TALOS-AMI): an investigator-initiated, open-label, multicentre, non-inferiority, randomised trial

Different clinical characteristics and impact of carbapenem-resistance on outcomes between Acinetobacter baumannii and Pseudomonas aeruginosa bacteraemia: a prospective observational study

Effect of mode and schedule of administration on carcinogenic effect of N-methyl-N?-nitro-N-nitrosoguanidine in rats

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