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Electrically Tunable Hysteretic Photonic Gels for Nonvolatile Display Pixels

Angewandte Chemie (International ed.), 2011-07, Vol.50 (28), p.6311-6314

International ed. in English, 2011

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Dielectrophoresis: From Molecular to Micrometer-Scale Analytes

Analytical chemistry (Washington), 2019-01, Vol.91 (1), p.277-295

2019

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Separation Phenomena in Tailored Micro- and Nanofluidic Environments

Annual review of analytical chemistry (Palo Alto, Calif.), 2019-06, Vol.12 (1), p.475

2019

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Deterministic Ratchet for Sub-micrometer (Bio)particle Separation

Analytical chemistry (Washington), 2018-04, Vol.90 (7), p.4370-4379

2018

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Quasi-Amorphous Colloidal Structures for Electrically Tunable Full-Color Photonic Pixels with Angle-Independency

Advanced materials (Weinheim), 2010-11, Vol.22 (44), p.4973-4977

2010

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Electric Triggering for Enhanced Control of Droplet Generation

Analytical chemistry (Washington), 2019-08, Vol.91 (15), p.9792-9799

2019

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Time-resolved serial femtosecond crystallography at the European XFEL

Nature methods, 2020-01, Vol.17 (1), p.73

2020

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3D printed droplet generation devices for serial femtosecond crystallography enabled by surface coating

Journal of applied crystallography, 2019-10, Vol.52 (5), p.997-1008

2019

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Nicolau syndrome involving whole ipsilateral limb induced by intramuscular administration of gentamycin

Indian journal of dermatology, venereology, and leprology, 2014-01, Vol.80 (1), p.96-96

2014

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Electrically Tunable Hysteretic Photonic Gels for Nonvolatile Display Pixels

Angewandte Chemie, 2011-07, Vol.123 (28), p.6435-6438

2011

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Electrically Tunable Hysteretic Photonic Gels for Nonvolatile Display Pixels

Angewandte Chemie, 2011-07, Vol.123 (28), p.6435-6438

2011

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Optical position-coded multiple-valued logic and arithmetic using liquid-crystal TVs and holograms

Optics communications, 1989-04, Vol.70 (5), p.379-383

1989

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GABARAPs and LC3s have opposite roles in regulating ULK1 for autophagy induction

Autophagy, 2020-04, Vol.16 (4), p.600-614

2020

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Quantitative Superresolution Microscopy Reveals the Critical Role of ULK1 Oligomeric States and Sub-Cellular Localization in Phagophore Maturation

Biophysical journal, 2020-02, Vol.118 (3), p.148a-148a

2020

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Elevation Estimation Algorithm for Low-Altitude Targets in Multipath Environment

Journal of Electromagnetic Engineering and Science, 2024-07, Vol.24 (4), p.341-349

2024

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Full surface heat transfer characteristics of rotor ventilation duct of a turbine generator

Applied thermal engineering, 2016-02, Vol.94, p.385-394

2016

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A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

IEEE journal of solid-state circuits, 2024, p.1-9

2024

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ULK1 forms distinct oligomeric states and nanoscopic structures during autophagy initiation

Science advances, 2023-09, Vol.9 (39), p.eadh4094-eadh4094

2023

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13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.234-236

2024

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Decomposition and Analysis of Process Variability Using Constrained Principal Component Analysis

IEEE transactions on semiconductor manufacturing, 2008-02, Vol.21 (1), p.55-62

2008

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Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.542-621

2007

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A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.540-620

2007

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Analysis of the Effects of Power Partitioning in LPDDR4x Package for Enhanced EMC Design

2024 IEEE 28th Workshop on Signal and Power Integrity (SPI), 2024, p.1-4

2024

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Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007, p.525-528

2007

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A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-4

2023

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Electrically Tunable Hysteretic Photonic Gels for Nonvolatile Display Pixels

Dielectrophoresis: From Molecular to Micrometer-Scale Analytes

Separation Phenomena in Tailored Micro- and Nanofluidic Environments

Deterministic Ratchet for Sub-micrometer (Bio)particle Separation

Quasi-Amorphous Colloidal Structures for Electrically Tunable Full-Color Photonic Pixels with Angle-Independency

Electric Triggering for Enhanced Control of Droplet Generation

Time-resolved serial femtosecond crystallography at the European XFEL

3D printed droplet generation devices for serial femtosecond crystallography enabled by surface coating

Nicolau syndrome involving whole ipsilateral limb induced by intramuscular administration of gentamycin

Electrically Tunable Hysteretic Photonic Gels for Nonvolatile Display Pixels

Electrically Tunable Hysteretic Photonic Gels for Nonvolatile Display Pixels

Optical position-coded multiple-valued logic and arithmetic using liquid-crystal TVs and holograms

GABARAPs and LC3s have opposite roles in regulating ULK1 for autophagy induction

Quantitative Superresolution Microscopy Reveals the Critical Role of ULK1 Oligomeric States and Sub-Cellular Localization in Phagophore Maturation

Elevation Estimation Algorithm for Low-Altitude Targets in Multipath Environment

Full surface heat transfer characteristics of rotor ventilation duct of a turbine generator

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

ULK1 forms distinct oligomeric states and nanoscopic structures during autophagy initiation

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

Decomposition and Analysis of Process Variability Using Constrained Principal Component Analysis

Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS

Analysis of the Effects of Power Partitioning in LPDDR4x Package for Enhanced EMC Design

Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

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