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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.238-240

2024

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13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.216-218

2019

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A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor

2012 IEEE International Solid-State Circuits Conference, 2012, p.390-392

2012

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152: Angiographic embolization for obstetric hemorrhage: a single center experience in 6 years′ period

American journal of obstetrics and gynecology, 2009-12, Vol.201 (6), p.S70-S70

2009

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.206-208

2018

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A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.444-446

2022

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A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.256-269

2023

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2,4,6-Trihydroxybenzaldehyde, a potential anti-obesity treatment, suppressed adipocyte differentiation in 3T3-L1 cells and fat accumulation induced by high-fat diet in C57BL/6 mice

Environmental toxicology and pharmacology, 2015-03, Vol.39 (2), p.962-968

2015

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22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.382-384

2020

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22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.334-336

2020

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23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.378-380

2019

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.390-391

2017

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3-Decylcatechol induces autophagy-mediated cell death through the IRE1α/JNK/p62 in hepatocellular carcinoma cells

Oncotarget, 2017-08, Vol.8 (35), p.58790-58800

2017

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3D PCL/fish collagen composite scaffolds incorporating osteogenic abalone protein hydrolysates for bone regeneration application: in vitro and in vivo studies

Journal of biomaterials science. Polymer ed., 2021-02, Vol.32 (3), p.355-371

2021

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A 3D-Printed Polycaprolactone/Marine Collagen Scaffold Reinforced with Carbonated Hydroxyapatite from Fish Bones for Bone Regeneration

Marine drugs, 2022-05, Vol.20 (6), p.344

2022

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492 Impact of Korean Ethnicity and Site of Treatment on Outcomes of Patients With Resectable Gastric Cancer

Gastroenterology (New York, N.Y. 1943), 2016-04, Vol.150 (4), p.S1184-S1184

2016

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A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration

2019 Symposium on VLSI Circuits, 2019, p.C114-C115

2019

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A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C182-C183

2015

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A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, p.281-284

2013

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A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12(3), 47, pp.270-277

2012

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A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

Journal of semiconductor technology and science, 2012, Vol.12 (3), p.270-277

2012

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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.157-166

2020

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7180 Incomplete pancreas divisum: is it merely a normal anatomic variant without clinical implication?

Gastrointestinal endoscopy, 2000-04, Vol.51 (4), p.AB287-AB287

2000

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778Influenza-like Illness in Korean Soldiers, 2011-2013: Comparison between military and community population

Open forum infectious diseases, 2014-12, Vol.1 (suppl_1), p.S220-S220

2014

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A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology

2011 IEEE International Solid-State Circuits Conference, 2011, p.212-213

2011

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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor

152: Angiographic embolization for obstetric hemorrhage: a single center experience in 6 years′ period

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

2,4,6-Trihydroxybenzaldehyde, a potential anti-obesity treatment, suppressed adipocyte differentiation in 3T3-L1 cells and fat accumulation induced by high-fat diet in C57BL/6 mice

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

3-Decylcatechol induces autophagy-mediated cell death through the IRE1α/JNK/p62 in hepatocellular carcinoma cells

3D PCL/fish collagen composite scaffolds incorporating osteogenic abalone protein hydrolysates for bone regeneration application: in vitro and in vivo studies

A 3D-Printed Polycaprolactone/Marine Collagen Scaffold Reinforced with Carbonated Hydroxyapatite from Fish Bones for Bone Regeneration

492 Impact of Korean Ethnicity and Site of Treatment on Outcomes of Patients With Resectable Gastric Cancer

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

7180 Incomplete pancreas divisum: is it merely a normal anatomic variant without clinical implication?

778Influenza-like Illness in Korean Soldiers, 2011-2013: Comparison between military and community population

A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology

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