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A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS

IEEE journal of solid-state circuits, 2017-10, Vol.52 (10), p.2735-2745

2017

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A low-noise fast-lock phase-locked loop with adaptive bandwidth control

IEEE journal of solid-state circuits, 2000-08, Vol.35 (8), p.1137-1145

2000

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A low-noise, 900-MHz VCO in 0.6-μm CMOS

IEEE journal of solid-state circuits, 1999-05, Vol.34 (5), p.586-591

1999

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Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two

IEEE transactions on circuits and systems. I, Regular papers, 2012-12, Vol.59 (12), p.2901-2910

2012

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A 192MHz differential XO based frequency quadrupler with sub-picosecond jitter in 28nm CMOS

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.59-62

2015

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A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.777-783

2001

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Quadrature direct digital frequency synthesizers using interpolation-based angle rotation

IEEE transactions on very large scale integration (VLSI) systems, 2004-07, Vol.12 (7), p.701-710

2004

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A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

IEEE journal of solid-state circuits, 2004-05, Vol.39 (5), p.847-851

2004

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A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

IEEE journal of solid-state circuits, 1997-02, Vol.32 (2), p.289-291

1997

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A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator

IEEE journal of solid-state circuits, 2003-10, Vol.38 (10), p.1609-1618

2003

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A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR

IEEE journal of solid-state circuits, 2004-11, Vol.39 (11), p.1853-1861

2004

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A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

IEEE journal of solid-state circuits, 2005-02, Vol.40 (2), p.462-471

2005

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A low-noise phase-locked loop design by loop bandwidth optimization

IEEE journal of solid-state circuits, 2000-06, Vol.35 (6), p.807-815

2000

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A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.918-925

2005

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A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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Low-jitter digital timing recovery techniques for CAP-based VDSL applications

IEEE journal of solid-state circuits, 2003-10, Vol.38 (10), p.1649-1656

2003

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Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2005-05, Vol.52 (5), p.885-893

2005

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Dual-loop DPLL gear-shifting algorithm for fast synchronization

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 1997-07, Vol.44 (7), p.577-586

KIM, B

1997

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A low-jitter mixed-mode DLL for high-speed DRAM applications

IEEE journal of solid-state circuits, 2000-10, Vol.35 (10), p.1430-1436

2000

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A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS

IEEE journal of solid-state circuits, 1991-04, Vol.26 (4), p.628-636

1991

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Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2005-04, Vol.E88-A (4), p.1084-1089

LIM, J.

2005

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An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2005-12, Vol.E88-A (12), p.3677-3680

LIM, J.

2005

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A 1.8-GHz self-calibrated phased-locked loop with precise I/Q matching

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.777-783

2001

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A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application

IEEE journal of solid-state circuits, 1997-05, Vol.32 (5), p.760-765, Article 760

1997

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Design of variable loop gains of dual-loop DPLL

IEEE transactions on communications, 1997-12, Vol.45 (12), p.1520-1522

1997

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A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS

A low-noise fast-lock phase-locked loop with adaptive bandwidth control

A low-noise, 900-MHz VCO in 0.6-μm CMOS

Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two

A 192MHz differential XO based frequency quadrupler with sub-picosecond jitter in 28nm CMOS

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

Quadrature direct digital frequency synthesizers using interpolation-based angle rotation

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator

A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

A low-noise phase-locked loop design by loop bandwidth optimization

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation

Low-jitter digital timing recovery techniques for CAP-based VDSL applications

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

Dual-loop DPLL gear-shifting algorithm for fast synchronization

A low-jitter mixed-mode DLL for high-speed DRAM applications

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS

Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators

An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications

A 1.8-GHz self-calibrated phased-locked loop with precise I/Q matching

A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application

Design of variable loop gains of dual-loop DPLL

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