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Texture Classification Using Dominant Neighborhood Structure
IEEE transactions on image processing, 2011-11, Vol.20 (11), p.3270-3279
2011
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A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.194-208
2011
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Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.50-63
2017
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2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology
IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.174-185
2009
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Accurate Estimation of SRAM Dynamic Stability
IEEE transactions on very large scale integration (VLSI) systems, 2008-12, Vol.16 (12), p.1639-1647
2008
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All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control
IEEE transactions on circuits and systems. I, Regular papers, 2011-09, Vol.58 (9), p.2017-2025
2011
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A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS
IEEE journal of solid-state circuits, 2014-04, Vol.49 (4), p.917-927
2014
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Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator
IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.18-30
2016
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Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays
IEEE journal of solid-state circuits, 2011-04, Vol.46 (4), p.797-805
2011
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Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference
IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.3-7
2018
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Formal derivation of optimal active shielding for low-power on-chip buses
IEEE transactions on computer-aided design of integrated circuits and systems, 2006-05, Vol.25 (5), p.821-836
2006
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Process, Temperature, and Supply-Noise Tolerant 45 ~nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits
IEEE journal of solid-state circuits, 2009-04, Vol.44 (4), p.1199-1208
2009
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SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus
IEEE transactions on circuits and systems. I, Regular papers, 2009-02, Vol.56 (2), p.384-394
2009
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An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization
IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.144-157
2019
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Characterization of Inverse Temperature Dependence in logic circuits
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-4
2012
Open Access
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Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling
IEEE transactions on very large scale integration (VLSI) systems, 2007-07, Vol.15 (7), p.746-757
2007
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Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS
IEEE solid-state circuits letters, 2019-09, Vol.2 (9), p.147-150
2019
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PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.352-353
2010
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Trading Off Cache Capacity for Low-Voltage Operation
IEEE MICRO, 2009-01, Vol.29 (1), p.96-103
2009
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A low-power high-performance current-mode multiport SRAM
IEEE transactions on very large scale integration (VLSI) systems, 2001-10, Vol.9 (5), p.590-598
2001
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Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS
2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-4
2015
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Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process
IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.751-758
2010
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Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques
IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-09, Vol.53 (9), p.1928-1933
2006
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A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2
2023
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Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses
IEEE transactions on circuits and systems. I, Regular papers, 2008-08, Vol.55 (7), p.1904-1910
2008
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