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ESD protection strategies in advanced CMOS SOI ICs

Microelectronics and reliability, 2007-09, Vol.47 (9), p.1313-1321

Khazhinsky, M.G.

2007

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Green's function method for waveguide and single impurity modes in 2D photonic crystals: H-polarization

Physics letters. A, 1998-01, Vol.237 (3), p.175-182

1998

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Short crack opening and prediction of fatigue notch factor

Engineering fracture mechanics, 1994-02, Vol.47 (3), p.417-422

Khazhinsky, Gregory M.

1994

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Electronic design automation (EDA) solutions for ESD-robust design and verification

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-8

2012

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Impurity modes from impurity clusters in photonic band structures

Journal of physics. Condensed matter, 1995-01, Vol.7 (2), p.447-462

1995

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Layout and bias options for maximizing V sub(t1) in cascoded NMOS output buffers

Microelectronics and reliability, 2001-11, Vol.41 (11), p.1751-1760

2001

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Advanced rail clamp networks for ESD protection

Microelectronics and reliability, 2005-02, Vol.45 (2), p.211-222

2005

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Latch-up characterization and checking of a 55 nm CMOS mixed voltage design

Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012, 2012, p.1-10

2012

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ESD protection of single output buffers in advanced CMOS technologies

Journal of electrostatics, 2006-02, Vol.64 (2), p.137-146

2006

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High performance, highly reliable FD/SOI I/O MOSFETs in contemporary high-performance PD/SOI CMOS

2007 IEEE International SOI Conference, 2007, p.83-84

2007

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Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

Microelectronics and reliability, 2002-06, Vol.42 (6), p.873-885

2002

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Protecting against Electrostatic Discharge (ESD) in Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs) Manufactured Using Silicon-on-Insulator (SOI) Technology

Silicon-on-Insulator (SOI) Technology - Manufacture and Applications, 2014, p.1-1

2014

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Direct numerical simulation of the large-signal RF behavior of power transistors

Proceedings of EDMO '96, 1996, p.14-19

1996

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Corner field effect of the CMP oxide recess in shallow trench isolation technology for high density flash memories

International Electron Devices Meeting. IEDM Technical Digest, 1997, p.665-668

1997

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Study of undoped channel FinFETs in active rail clamp ESD networks

2008 IEEE International Reliability Physics Symposium, 2008, p.262-269

2008

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Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

2004 Electrical Overstress/Electrostatic Discharge Symposium, 2004, p.1-10

2004

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Comprehensive ESD protection for flip-chip products in a dual gate oxide 65nm CMOS technology

2006 Electrical Overstress/Electrostatic Discharge Symposium, 2006, p.186-195

2006

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ESD protection for advanced CMOS SOI technologies

2005 Electrical Overstress/Electrostatic Discharge Symposium, 2005, p.1-10

2005

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Contributor contact details

Silicon-on-insulator (SOI) Technology, 2014, p.xi-xiii

2014

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Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies

2003 Electrical Overstress/Electrostatic Discharge Symposium, 2003, p.1-10

2003

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Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

2001 Electrical Overstress/Electrostatic Discharge Symposium, 2001, p.81-94

2001

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ESD protection strategies in advanced CMOS SOI ICs

Green's function method for waveguide and single impurity modes in 2D photonic crystals: H-polarization

Short crack opening and prediction of fatigue notch factor

Electronic design automation (EDA) solutions for ESD-robust design and verification

Impurity modes from impurity clusters in photonic band structures

Layout and bias options for maximizing V sub(t1) in cascoded NMOS output buffers

Advanced rail clamp networks for ESD protection

Latch-up characterization and checking of a 55 nm CMOS mixed voltage design

ESD protection of single output buffers in advanced CMOS technologies

High performance, highly reliable FD/SOI I/O MOSFETs in contemporary high-performance PD/SOI CMOS

Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

Protecting against Electrostatic Discharge (ESD) in Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs) Manufactured Using Silicon-on-Insulator (SOI) Technology

Direct numerical simulation of the large-signal RF behavior of power transistors

Corner field effect of the CMP oxide recess in shallow trench isolation technology for high density flash memories

Study of undoped channel FinFETs in active rail clamp ESD networks

Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

Comprehensive ESD protection for flip-chip products in a dual gate oxide 65nm CMOS technology

ESD protection for advanced CMOS SOI technologies

Contributor contact details

Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies

Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

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