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Efficient On-Chip Crosstalk Avoidance CODEC Design

IEEE transactions on very large scale integration (VLSI) systems, 2009-04, Vol.17 (4), p.551-560

2009

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A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

IEEE transactions on very large scale integration (VLSI) systems, 2009-02, Vol.17 (2), p.269-277

2009

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A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic

IEEE transactions on very large scale integration (VLSI) systems, 2008-03, Vol.16 (3), p.326-331

2008

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Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

IEEE transactions on very large scale integration (VLSI) systems, 2009-06, Vol.17 (6), p.781-792

2009

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A Timing-Driven Approach to Synthesize Fast Barrel Shifters

IEEE transactions on circuits and systems. II, Express briefs, 2008-01, Vol.55 (1), p.31-35

2008

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A Predictably Low-Leakage ASIC Design Style

IEEE transactions on very large scale integration (VLSI) systems, 2007-03, Vol.15 (3), p.276-285

2007

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Dynamically De-Skewable Clock Distribution Methodology

IEEE transactions on very large scale integration (VLSI) systems, 2008-09, Vol.16 (9), p.1220-1229

2008

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An efficient and regular routing methodology for datapath designs using net regularity extraction

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-01, Vol.21 (1), p.93-101

2002

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SPFD-based wire removal in standard-cell and network-of-PLA circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-07, Vol.23 (7), p.1020-1030

2004

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Towards acceleration of fault simulation using graphics processing units

2008 45th ACM/IEEE Design Automation Conference, 2008, p.822-827

2008

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Accelerating statistical static timing analysis using graphics processing units

2009 Asia and South Pacific Design Automation Conference, 2009, p.260-265

2009

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Clock Distribution Scheme using Coplanar Transmission Lines

2008 Design, Automation and Test in Europe, 2008, p.985-990

2008

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A novel, highly SEU tolerant digital circuit design approach

2008 IEEE International Conference on Computer Design, 2008, p.14-20

2008

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3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit

2009 IEEE International Conference on Computer Design, 2009, p.498-504

2009

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A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements

2008 Design, Automation and Test in Europe, 2008, p.354-359

2008

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Forbidden transition free crosstalk avoidance CODEC design

2008 45th ACM/IEEE Design Automation Conference, 2008, p.986-991

2008

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A design approach for radiation-hard digital electronics

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.773-778

2006

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Fault table generation using Graphics Processing Units

2009 IEEE International High Level Design Validation and Test Workshop, 2009, p.60-67

2009

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Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

IET computers & digital techniques, 2008-05, Vol.2 (3), p.214-229

2008

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An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-6

2007

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Computing during supply voltage switching in DVS enabled real-time processors

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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Generalized buffering of PTL logic stages using Boolean division

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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A fast, analytical estimator for the SEU-induced pulse width in combinational designs

2008 45th ACM/IEEE Design Automation Conference, 2008, p.918-923

2008

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A radiation tolerant Phase Locked Loop design for digital electronics

2009 IEEE International Conference on Computer Design, 2009, p.505-510

2009

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Exploiting crosstalk to speed up on-chip buses

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.778-783 Vol.2

2004

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Efficient On-Chip Crosstalk Avoidance CODEC Design

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

A Timing-Driven Approach to Synthesize Fast Barrel Shifters

A Predictably Low-Leakage ASIC Design Style

Dynamically De-Skewable Clock Distribution Methodology

An efficient and regular routing methodology for datapath designs using net regularity extraction

SPFD-based wire removal in standard-cell and network-of-PLA circuits

Towards acceleration of fault simulation using graphics processing units

Accelerating statistical static timing analysis using graphics processing units

Clock Distribution Scheme using Coplanar Transmission Lines

A novel, highly SEU tolerant digital circuit design approach

3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements

Forbidden transition free crosstalk avoidance CODEC design

A design approach for radiation-hard digital electronics

Fault table generation using Graphics Processing Units

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification

Computing during supply voltage switching in DVS enabled real-time processors

Generalized buffering of PTL logic stages using Boolean division

A fast, analytical estimator for the SEU-induced pulse width in combinational designs

A radiation tolerant Phase Locked Loop design for digital electronics

Exploiting crosstalk to speed up on-chip buses

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