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Stochastic-HD: Leveraging Stochastic Computing on the Hyper-Dimensional Computing Pipeline

Frontiers in neuroscience, 2022-05, Vol.16, p.867192-867192

2022

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A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

IEEE transactions on circuits and systems. I, Regular papers, 2018-07, Vol.65 (7), p.2196-2209

2018

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Swapping Metagenomics Preprocessing Pipeline Components Offers Speed and Sensitivity Increases

mSystems, 2022-04, Vol.7 (2), p.e0137821-e0137821

2022

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OpenHD: A GPU-Powered Framework for Hyperdimensional Computing

IEEE transactions on computers, 2022-11, Vol.71 (11), p.2753-2765

2022

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An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-03, Vol.38 (3), p.466-479

2019

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PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

IEEE transactions on computers, 2017-06, Vol.66 (6), p.982-995

2017

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RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019, p.1-6

2019

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Prive-HD: Privacy-Preserved Hyperdimensional Computing

2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, p.1-6

2020

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Hardware-Algorithm Co-design for Efficient and Privacy-Preserved Edge Computing

Khaleghi, Behnam

2022

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tiny-HD: Ultra-Efficient Hyperdimensional Computing Engine for IoT Applications

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, p.408-413

2021

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HyperSpikeASIC : Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.3997-4010

2023

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SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019, p.190-198

2019

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Estimating and Mitigating Aging Effects in Routing Network of FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2019-03, Vol.27 (3), p.651-664

2019

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Accelerating Event-based Workloads with HyperDimensional Computing and Spiking Neural Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-03, p.1-1

2023

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TermiNETor: Early Convolution Termination for Efficient Deep Neural Networks

2022 IEEE 40th International Conference on Computer Design (ICCD), 2022, p.635-643

2022

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A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices

IEEE transactions on very large scale integration (VLSI) systems, 2015-09, Vol.23 (9), p.1868-1878

2015

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Utilizing Hyperdimensional Computing for a More Robust and Efficient Machine Learning System

ACM transactions on embedded computing systems, 2022-11, Vol.21 (6), p.1-25, Article 78

2022

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Reliability-aware design to suppress aging

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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FPGA Energy Efficiency by Leveraging Thermal Margin

2019 IEEE 37th International Conference on Computer Design (ICCD), 2019, p.376-384

2019

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Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

IEEE transactions on very large scale integration (VLSI) systems, 2016-12, Vol.24 (12), p.3489-3498

2016

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Hierarchical, Distributed and Brain-Inspired Learning for Internet of Things Systems

2023 IEEE 43rd International Conference on Distributed Computing Systems (ICDCS), 2023, p.511-522

2023

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FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic

IEEE embedded systems letters, 2015-06, Vol.7 (2), p.46-50

2015

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A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.1342-1347

2017

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TruLook: A Framework for Configurable GPU Approximation

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, p.487-490

2021

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Thermal-Aware Design and Flow for FPGA Performance Improvement

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.342-347

2019

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Stochastic-HD: Leveraging Stochastic Computing on the Hyper-Dimensional Computing Pipeline

A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

Swapping Metagenomics Preprocessing Pipeline Components Offers Speed and Sensitivity Increases

OpenHD: A GPU-Powered Framework for Hyperdimensional Computing

An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors

PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment

Prive-HD: Privacy-Preserved Hyperdimensional Computing

Hardware-Algorithm Co-design for Efficient and Privacy-Preserved Edge Computing

tiny-HD: Ultra-Efficient Hyperdimensional Computing Engine for IoT Applications

HyperSpikeASIC : Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks

SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing

Estimating and Mitigating Aging Effects in Routing Network of FPGAs

Accelerating Event-based Workloads with HyperDimensional Computing and Spiking Neural Networks

TermiNETor: Early Convolution Termination for Efficient Deep Neural Networks

A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices

Utilizing Hyperdimensional Computing for a More Robust and Efficient Machine Learning System

Reliability-aware design to suppress aging

FPGA Energy Efficiency by Leveraging Thermal Margin

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Hierarchical, Distributed and Brain-Inspired Learning for Internet of Things Systems

FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic

A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era

TruLook: A Framework for Configurable GPU Approximation

Thermal-Aware Design and Flow for FPGA Performance Improvement

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