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The critical oxide thickness for Pb-free reflow soldering on Cu substrate

Thin solid films, 2012-06, Vol.520 (16), p.5346-5352

2012

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Thermal Stress of Surface Oxide Layer on Micro Solder Bumps During Reflow

Journal of electronic materials, 2015-02, Vol.44 (2), p.744-750

2015

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Reactions of Sn-4.0Ag-0.5Cu on Cu and Electroless Ni Substrate in Premelting Soldering Process

Journal of electronic materials, 2013-06, Vol.42 (6), p.1254-1259

2013

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Roles of phosphorous in Sn4Ag0.5Cu solder reaction with electrolytic Ni–Au

Journal of alloys and compounds, 2012-10, Vol.539, p.57-62

2012

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Direct evidence for a Cu-enriched region at the boundary between Cu6Sn5 and Cu3Sn during Cu/Sn reaction

Scripta materialia, 2010-07, Vol.63 (2), p.258-260

2010

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Challenges of large Fan out multi-chip module and fine Cu line space

2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.1140-1145

2020

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Mechanisms and solutions to the brittle solder joint in electroless Ni plating

Microelectronics and reliability, 2016-10, Vol.65, p.173-177

2016

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3D FO package technology using bridge die for high number of chiplets integration

2023 24th International Conference on Electronic Packaging Technology (ICEPT), 2023, p.1-6

2023

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Lidless and lidded Flip Chip Packages for Advanced Applications

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 2020, p.104-111

2020

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Origin and evolution of voids in electroless Ni during soldering reaction

Acta materialia, 2012-06, Vol.60 (11), p.4586-4593

2012

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Generational changes of flip chip interconnection technology

2017 12th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2017, p.306-310

2017

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The challenge of Fan-out WLP in different process flow

2018 13th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2018, p.47-50

2018

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Board Level Reliability of Thinner Stacking Chips Package with Through Silicon Via Interposer

2018 13th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2018, p.237-240

2018

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Direct evidence for a Cu-enriched region at the boundary between Cu 6Sn 5 and Cu 3Sn during Cu/Sn reaction

Scripta materialia, 2010, Vol.63 (2), p.258-260

2010

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Characterizations of micro bump undercuts for chiplets integrated packaging

2022 23rd International Conference on Electronic Packaging Technology (ICEPT), 2022, p.1-4

2022

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Overcome high density substrate shortage by using Fan Out Chip Module

2022 23rd International Conference on Electronic Packaging Technology (ICEPT), 2022, p.1-4

2022

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Scalable Chiplet package using Fan-Out Embedded Bridge

2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.14-18

2020

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Electrical Performances of Fan-Out Embedded Bridge

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.2030-2034

2021

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The interactions of lead (Pb) in lead free solder (Sn/Ag/Cu) system

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345), 2002, p.168-175

2002

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Highly Thermal Dissipation for Large HPC Package Using Liquid Metal Materials

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.1102-1108

2021

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LTD PKG. (Liquid Thermal Dissipation Package) Technology

2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2019, p.146-149

2019

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Comparison of 3D Packages with 20 \mu \mathrm bump pitch using reflow soldering and thermal compression bonding

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.481-486

2021

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3D Micro Bump Interface Enabling Top Die Interconnect to True Circuit Through Silicon Via Wafer

2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.1888-1893

2020

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Construction of FO-MCM with C4 Bumps Built First Using Chip Last Assembly Technology

2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, p.7-13

2019

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Process Induced Wafer Warpage Optimization for Multi-chip Integration on Wafer Level Molded Wafer

2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, p.1287-1293

2019

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The critical oxide thickness for Pb-free reflow soldering on Cu substrate

Thermal Stress of Surface Oxide Layer on Micro Solder Bumps During Reflow

Reactions of Sn-4.0Ag-0.5Cu on Cu and Electroless Ni Substrate in Premelting Soldering Process

Roles of phosphorous in Sn4Ag0.5Cu solder reaction with electrolytic Ni–Au

Direct evidence for a Cu-enriched region at the boundary between Cu6Sn5 and Cu3Sn during Cu/Sn reaction

Challenges of large Fan out multi-chip module and fine Cu line space

Mechanisms and solutions to the brittle solder joint in electroless Ni plating

3D FO package technology using bridge die for high number of chiplets integration

Lidless and lidded Flip Chip Packages for Advanced Applications

Origin and evolution of voids in electroless Ni during soldering reaction

Generational changes of flip chip interconnection technology

The challenge of Fan-out WLP in different process flow

Board Level Reliability of Thinner Stacking Chips Package with Through Silicon Via Interposer

Direct evidence for a Cu-enriched region at the boundary between Cu 6Sn 5 and Cu 3Sn during Cu/Sn reaction

Characterizations of micro bump undercuts for chiplets integrated packaging

Overcome high density substrate shortage by using Fan Out Chip Module

Scalable Chiplet package using Fan-Out Embedded Bridge

Electrical Performances of Fan-Out Embedded Bridge

The interactions of lead (Pb) in lead free solder (Sn/Ag/Cu) system

Highly Thermal Dissipation for Large HPC Package Using Liquid Metal Materials

LTD PKG. (Liquid Thermal Dissipation Package) Technology

Comparison of 3D Packages with 20 \mu \mathrm bump pitch using reflow soldering and thermal compression bonding

3D Micro Bump Interface Enabling Top Die Interconnect to True Circuit Through Silicon Via Wafer

Construction of FO-MCM with C4 Bumps Built First Using Chip Last Assembly Technology

Process Induced Wafer Warpage Optimization for Multi-chip Integration on Wafer Level Molded Wafer

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