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Practical parallel imaging compressed sensing MRI: Summary of two years of experience in accelerating body MRI of pediatric patients

2011 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2011-12, Vol.2011, p.1039-1043

2011

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System-level design: orthogonalization of concerns and platform-based design

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-12, Vol.19 (12), p.1523-1543

2000

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Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-05, Vol.21 (5), p.544-553

2002

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Impact of small process geometries on microarchitectures in systems on a chip

Proceedings of the IEEE, 2001-04, Vol.89 (4), p.467-489

2001

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A global wiring paradigm for deep submicron design

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-02, Vol.19 (2), p.242-252

2000

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Addressing the system-on-a-chip interconnect woes through communication-based design

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.667-672

2001

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OCCOM-efficient computation of observability-based code coverage metrics for functional verification

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-08, Vol.20 (8), p.1003-1015

2001

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NP-Click: a productive software development approach for network processors

IEEE MICRO, 2004-09, Vol.24 (5), p.45-54

2004

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Functional vector generation for HDL models using linear programming and Boolean satisfiability

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-08, Vol.20 (8), p.994-1002

2001

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Rethinking deep-submicron circuit design

Computer (Long Beach, Calif.), 1999-11, Vol.32 (11), p.25-33

1999

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Limitations and challenges of computer-aided design technology for CMOS VLSI

Proceedings of the IEEE, 2001-03, Vol.89 (3), p.341-365

2001

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Functional vector generation for HDL models using linear programming and 3-satisfiability

Annual ACM IEEE Design Automation Conference: Proceedings of the 35th annual conference on Design automation; 15-19 June 1998, 1998, p.528-533

1998

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Closing the gap between ASIC and custom: an ASIC perspective

Annual ACM IEEE Design Automation Conference: Proceedings of the 37th conference on Design automation; 05-09 June 2000, 2000, p.637-642

2000

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Bus encoding to prevent crosstalk delay

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2001, p.57-63

2001

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A quick safari through the reconfiguration jungle

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.172-177

2001

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From ASIC to ASIP: the next design discontinuity

Proceedings, IEEE International Conference on Computer Design, 2002, p.84-90

2002

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A general probabilistic framework for worst case timing analysis

Proceedings - ACM IEEE Design Automation Conference, 2002, p.556-561

2002

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Estimation of average switching activity in combinational logic circuits using symbolic simulation

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-01, Vol.16 (1), p.121-127

1997

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Accelerating Value-at-Risk estimation on highly parallel architectures

Concurrency and computation, 2012-06, Vol.24 (8), p.895-907

2012

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Closing the power gap between ASIC and custom: an ASIC perspective

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.275-280

2005

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Delay-fault test generation and synthesis for testability under a standard scan design methodology

IEEE transactions on computer-aided design of integrated circuits and systems, 1993-08, Vol.12 (8), p.1217-1231

1993

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Coverage metrics for functional validation of hardware designs

IEEE design & test of computers, 2001-07, Vol.18 (4), p.36-45

2001

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Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-03, Vol.11 (3), p.373-383

1992

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Fast $\ell_1$-SPIRiT Compressed Sensing Parallel Imaging MRI: Scalable Parallel Implementation and Clinically Feasible Runtime

IEEE transactions on medical imaging, 2012-06, Vol.31 (6), p.1250-1262

2012

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Fast \ell1 -SPIRiT Compressed Sensing Parallel Imaging MRI: Scalable Parallel Implementation and Clinically Feasible Runtime

IEEE transactions on medical imaging, 2012-06, Vol.31 (6), p.1250-1262

2012

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Practical parallel imaging compressed sensing MRI: Summary of two years of experience in accelerating body MRI of pediatric patients

System-level design: orthogonalization of concerns and platform-based design

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

Impact of small process geometries on microarchitectures in systems on a chip

A global wiring paradigm for deep submicron design

Addressing the system-on-a-chip interconnect woes through communication-based design

OCCOM-efficient computation of observability-based code coverage metrics for functional verification

NP-Click: a productive software development approach for network processors

Functional vector generation for HDL models using linear programming and Boolean satisfiability

Rethinking deep-submicron circuit design

Limitations and challenges of computer-aided design technology for CMOS VLSI

Functional vector generation for HDL models using linear programming and 3-satisfiability

Closing the gap between ASIC and custom: an ASIC perspective

Bus encoding to prevent crosstalk delay

A quick safari through the reconfiguration jungle

From ASIC to ASIP: the next design discontinuity

A general probabilistic framework for worst case timing analysis

Estimation of average switching activity in combinational logic circuits using symbolic simulation

Accelerating Value-at-Risk estimation on highly parallel architectures

Closing the power gap between ASIC and custom: an ASIC perspective

Delay-fault test generation and synthesis for testability under a standard scan design methodology

Coverage metrics for functional validation of hardware designs

Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation

Fast $\ell_1$-SPIRiT Compressed Sensing Parallel Imaging MRI: Scalable Parallel Implementation and Clinically Feasible Runtime

Fast \ell1 -SPIRiT Compressed Sensing Parallel Imaging MRI: Scalable Parallel Implementation and Clinically Feasible Runtime

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