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IPM-RED: combining higher-order masking with robust error detection

Journal of cryptographic engineering, 2021-06, Vol.11 (2), p.147-160

2021

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Silicon Proven 1.29 μm × 1.8 μm 65nm Sub-Vt Optical Sensor for Hardware Security Applications

IEEE access, 2023, Vol.11, p.136269-136278

2023

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Error control scheme for malicious and natural faults in cryptographic modules

Journal of cryptographic engineering, 2020-11, Vol.10 (4), p.321-336

2020

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A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF

IEEE access, 2020, Vol.8, p.219137-219150

2020

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Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

IEEE access, 2021, Vol.9, p.91764-91776

2021

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Constructive Bounds on the Capacity of Parallel Asynchronous Skew-Free Channels With Glitches

IEEE transactions on information theory, 2020-07, Vol.66 (7), p.4026-4037

2020

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On Codes for Detecting Address and Data Manipulations in Memory Arrays

IEEE transactions on information theory, 2024-08, Vol.70 (8), p.5544-5551

2024

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A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits

IEEE access, 2017-01, Vol.5, p.24797-24809

2017

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On the Existence of Security Enhancing Converter Designs for Multi-Level Memories

IEEE transactions on circuits and systems. II, Express briefs, 2020-06, Vol.67 (6), p.1119-1123

2020

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Reliable Communications Across Parallel Asynchronous Channels With Arbitrary Skews

IEEE transactions on information theory, 2017-02, Vol.63 (2), p.1120-1129

2017

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Protecting Multi-Level Memories From Jamming Using Q-ary Expurgated Robust Codes

IEEE transactions on dependable and secure computing, 2021-03, Vol.18 (2), p.936-948

2021

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Relations Between the Entropy of a Source and the Error Masking Probability for Security-Oriented Codes

IEEE transactions on communications, 2015-01, Vol.63 (1), p.206-214

2015

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An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9 Key Error Probability

IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4855-4868

2020

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Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-01, Vol.30 (1), p.31-44

2011

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A 7T Security Oriented SRAM Bitcell

IEEE transactions on circuits and systems. II, Express briefs, 2019-08, Vol.66 (8), p.1396-1400

2019

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Data-Dependent Delays as a Barrier Against Power Attacks

IEEE transactions on circuits and systems. I, Regular papers, 2015-08, Vol.62 (8), p.2069-2078

2015

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A new class of security oriented error correcting robust codes

Cryptography and communications, 2019-09, Vol.11 (5), p.965-978

2019

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Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information

IEEE transactions on very large scale integration (VLSI) systems, 2018-01, Vol.26 (1), p.82-95

2018

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DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes

IEEE transactions on circuits and systems. I, Regular papers, 2015-01, Vol.62 (1), p.149-156

2015

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High Rate Robust Codes with Low Implementation Complexity

IEEE transactions on dependable and secure computing, 2019-05, Vol.16 (3), p.511-520

2019

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Nonlinear Code-Based Low-Overhead Fine-Grained Control Flow Checking

IEEE transactions on computers, 2022-03, Vol.71 (3), p.658-669

2022

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CPA Secured Data-Dependent Delay-Assignment Methodology

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.608-620

2017

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Robust Generalized Punctured Cubic Codes

IEEE transactions on information theory, 2014-05, Vol.60 (5), p.2813-2822

2014

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A Method to Improve Reliability in a 65-nm SRAM PUF Array

IEEE solid-state circuits letters, 2018-06, Vol.1 (6), p.138-141

2018

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Silicon Proven 1.8~\mu\text\times\,9.2\,\,\mu\text 65-nm Digital Bit Generator for Hardware Security Applications

IEEE transactions on circuits and systems. II, Express briefs, 2019-10, Vol.66 (10), p.1713-1717

2019

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IPM-RED: combining higher-order masking with robust error detection

Silicon Proven 1.29 μm × 1.8 μm 65nm Sub-Vt Optical Sensor for Hardware Security Applications

Error control scheme for malicious and natural faults in cryptographic modules

A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Constructive Bounds on the Capacity of Parallel Asynchronous Skew-Free Channels With Glitches

On Codes for Detecting Address and Data Manipulations in Memory Arrays

A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits

On the Existence of Security Enhancing Converter Designs for Multi-Level Memories

Reliable Communications Across Parallel Asynchronous Channels With Arbitrary Skews

Protecting Multi-Level Memories From Jamming Using Q-ary Expurgated Robust Codes

Relations Between the Entropy of a Source and the Error Masking Probability for Security-Oriented Codes

An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9 Key Error Probability

Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients

A 7T Security Oriented SRAM Bitcell

Data-Dependent Delays as a Barrier Against Power Attacks

A new class of security oriented error correcting robust codes

Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes

High Rate Robust Codes with Low Implementation Complexity

Nonlinear Code-Based Low-Overhead Fine-Grained Control Flow Checking

CPA Secured Data-Dependent Delay-Assignment Methodology

Robust Generalized Punctured Cubic Codes

A Method to Improve Reliability in a 65-nm SRAM PUF Array

Silicon Proven 1.8~\mu\text\times\,9.2\,\,\mu\text 65-nm Digital Bit Generator for Hardware Security Applications

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