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Latchup Risk in a 4H-SiC Process

IEEE transactions on electron devices, 2024-05, Vol.71 (5), p.3424-3428

2024

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Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process

IEEE transactions on biomedical circuits and systems, 2021-06, Vol.15 (3), p.568-579

2021

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Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O With Low-Voltage Biased NBL Isolation Ring in a 0.18-μm BCD Technology

IEEE transactions on electron devices, 2024-03, Vol.71 (3), p.2224-2227

2024

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Design of Bi-Directional ESD Protection Circuit With Uni-Directional ESD Device in BCD Technology

IEEE transactions on electron devices, 2023-10, Vol.70 (10), p.5028-5035

2023

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Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1461-1470

2021

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Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources

IEEE electron device letters, 2021-03, Vol.42 (3), p.395-397

2021

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Schottky-Embedded Silicon-Controlled Rectifier With High Holding Voltage Realized in a 0.18-μm Low-Voltage CMOS Process

IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1764-1771

2021

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The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests

IEEE transactions on electron devices, 2021-05, Vol.68 (5), p.2152-2159

2021

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Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation

IEEE transactions on circuits and systems. I, Regular papers, 2020-11, Vol.67 (11), p.4122-4131

2020

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A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

IEEE transactions on biomedical circuits and systems, 2016-12, Vol.10 (6), p.1087-1099

2016

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The Parasitic Latch-Up Path From Substrate P⁺ Guard Ring to the NMOS in Deep N-Well Operating With Negative Voltage Sources

IEEE electron device letters, 2022-04, Vol.43 (4), p.604-606

2022

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Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage FlexRay Applications

IEEE transactions on electron devices, 2022-10, Vol.69 (10), p.5713-5721

2022

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A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

IEEE journal of solid-state circuits, 2018-11, Vol.53 (11), p.3314-3326

2018

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An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process

IEEE transactions on circuits and systems. I, Regular papers, 2019-09, Vol.66 (9), p.3437-3444

2019

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Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

IEEE transactions on electron devices, 2019-04, Vol.66 (4), p.1648-1655

2019

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Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

IEEE transactions on electron devices, 2020-01, Vol.67 (1), p.40-46

2020

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Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications

IEEE transactions on biomedical circuits and systems, 2020-10, Vol.14 (5), p.961-970

2020

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On-Chip Over-Voltage Protection Design Against Surge Events on the CC Pin of USB Type-C Interface

IEEE transactions on electron devices, 2020-07, Vol.67 (7), p.2702-2709

2020

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Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process

IEEE transactions on electron devices, 2020-07, Vol.67 (7), p.2725-2731

2020

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Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation

IEEE transactions on biomedical circuits and systems, 2023-04, Vol.17 (2), p.1-14

2023

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Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process

IEEE transactions on electron devices, 2013-10, Vol.60 (10), p.3500-3507

2013

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Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS), 2024, p.1-6

2024

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A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control

IEEE journal of solid-state circuits, 2014-01, Vol.49 (1), p.232-247

2014

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A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs

IEEE transactions on circuits and systems. I, Regular papers, 2023-06, Vol.70 (6), p.2257-2270

2023

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ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

IEEE transactions on electron devices, 2016-05, Vol.63 (5), p.1996-2002

2016

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Latchup Risk in a 4H-SiC Process

Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process

Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O With Low-Voltage Biased NBL Isolation Ring in a 0.18-μm BCD Technology

Design of Bi-Directional ESD Protection Circuit With Uni-Directional ESD Device in BCD Technology

Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources

Schottky-Embedded Silicon-Controlled Rectifier With High Holding Voltage Realized in a 0.18-μm Low-Voltage CMOS Process

The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests

Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

The Parasitic Latch-Up Path From Substrate P⁺ Guard Ring to the NMOS in Deep N-Well Operating With Negative Voltage Sources

Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage FlexRay Applications

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process

Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications

On-Chip Over-Voltage Protection Design Against Surge Events on the CC Pin of USB Type-C Interface

Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process

Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation

Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process

Test Structures of Cross-Domain Interface Circuits with Deep N-Well Layout to Improve CDM ESD Robustness

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control

A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs

ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

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