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A systolic array technique for determining common approximate substrings

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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A Methodology for Rapid Optimization of HandelC Specifications

2009 IEEE/IFIP International Symposium on Rapid System Prototyping, 2009, p.81-87

2009

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A design flow for optimal circuit design using resource and timing estimation

2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2009, p.227-233

2009

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Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems

IET computers & digital techniques, 2009-05, Vol.3 (3), p.247-258

2009

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An OpenMP-based circuit design tool: Customizable bit-width

2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2009, p.17-22

2009

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Design & Implementation of the Interface of a Hardware/Software Co-Designed Virtual Machine

2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2007, p.109-112

2007

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Rapid Prototyping Projection Algorithms with FPGA Technology

2009 IEEE/IFIP International Symposium on Rapid System Prototyping, 2009, p.95-101

2009

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Development of a Co-Design Learning Environment

2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2007, p.367-370

2007

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Application Specific Instruction Sets and their Impact on the Design Space Requirements of a Hardware Java Virtual Machine

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, 2008, p.175-181

2008

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Codesign of a Computationally Intensive Problem in GF(3)

18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), 2007, p.10-16

2007

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Incremental communication for multilayer neural networks in a field programmable gate array

PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005, 2005, p.605-608

2005

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Loop sensitive context switching between partitions in a co-design virtual machine

PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005, 2005, p.281-284

2005

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Periodic licensing of FPGA based intellectual property

2006 IEEE International Conference on Field Programmable Technology, 2006, p.357-360

2006

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A Partitioning Analysis of the .NET Common Language Runtime

14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems (ECBS'07), 2007, p.317-326

2007

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An embedded decryption/decompression engine using Handel-C

2008 International Symposium on Industrial Embedded Systems, 2008, p.51-57

2008

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An Embedded Implementation of the Microsoft Common Language Infrastructure

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007, p.165-172

2007

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Automatic Identification of Parallelism in Handel-C

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.660-664

2008

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An Embedded Java Virtual Machine Using Network-on-Chip Design

Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), 2006, p.149-155

2006

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A Handel-C Implementation of a Computationally Intensive Problem in GF(3)

2008 International Conference on Advances in Electronics and Micro-electronics, 2008, p.36-41

2008

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Hardware architecture for Java in a hardware/software co-design of the virtual machine

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, 2002, p.20-27

2002

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Branch sensitive context switching between partitions in a hardware/software co-design of the Java virtual machine

2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) (Cat. No.03CH37490), 2003, Vol.2, p.642-645 vol.2

Kent, K.B.

2003

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Thread-level parallel execution in co-designed virtual machines

16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 2005, p.249-251

2005

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Analysis of Variable Reordering on the QMDD Representation of Quantum Circuits

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007, p.347-352

2007

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Analysis of incremental communication for multilayer neural networks on a field programmable gate array

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005, p.252-254

2005

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Reconfigurable architecture requirements for co-designed virtual machines

Proceedings International Parallel and Distributed Processing Symposium, 2003, p.6 pp.

2003

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A systolic array technique for determining common approximate substrings

A Methodology for Rapid Optimization of HandelC Specifications

A design flow for optimal circuit design using resource and timing estimation

Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems

An OpenMP-based circuit design tool: Customizable bit-width

Design & Implementation of the Interface of a Hardware/Software Co-Designed Virtual Machine

Rapid Prototyping Projection Algorithms with FPGA Technology

Development of a Co-Design Learning Environment

Application Specific Instruction Sets and their Impact on the Design Space Requirements of a Hardware Java Virtual Machine

Codesign of a Computationally Intensive Problem in GF(3)

Incremental communication for multilayer neural networks in a field programmable gate array

Loop sensitive context switching between partitions in a co-design virtual machine

Periodic licensing of FPGA based intellectual property

A Partitioning Analysis of the .NET Common Language Runtime

An embedded decryption/decompression engine using Handel-C

An Embedded Implementation of the Microsoft Common Language Infrastructure

Automatic Identification of Parallelism in Handel-C

An Embedded Java Virtual Machine Using Network-on-Chip Design

A Handel-C Implementation of a Computationally Intensive Problem in GF(3)

Hardware architecture for Java in a hardware/software co-design of the virtual machine

Branch sensitive context switching between partitions in a hardware/software co-design of the Java virtual machine

Thread-level parallel execution in co-designed virtual machines

Analysis of Variable Reordering on the QMDD Representation of Quantum Circuits

Analysis of incremental communication for multilayer neural networks on a field programmable gate array

Reconfigurable architecture requirements for co-designed virtual machines

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