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Interconnect Routing for Large-Scale RSFQ Circuits

IEEE transactions on applied superconductivity, 2019-08, Vol.29 (5), p.1-5

2019

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A full-custom design flow and a top-down RTL-to-GDS flow for adiabatic quantum-flux-parametron logic using a commercial EDA design suite

IEEE transactions on applied superconductivity, 2023-08, Vol.33 (5), p.1-7

2023

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Challenges and the status of superconducting single flux quantum technology

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.1781-1787

2019

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Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits

Journal of electronic testing, 2024-10

2024

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Repeater Insertion in SFQ Interconnect

IEEE transactions on applied superconductivity, 2020-12, Vol.30 (8), p.1-8

2020

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Splitter Trees in Single Flux Quantum Circuits

IEEE transactions on applied superconductivity, 2021-08, Vol.31 (5), p.1-6

2021

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Josephson Junction Stuck-At Fault Detection in SFQ Circuits

IEEE transactions on applied superconductivity, 2023-09, Vol.33 (6), p.1-8

2023

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Observations in Use of a Tunnel Junction Model in Simulations of Josephson Digital Circuits

IEEE transactions on applied superconductivity, 2023-08, Vol.33 (5), p.1-9

2023

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Low Power and Power Management for CMOS : An EDA Perspective : Device technologies and circuit techniques for power management

IEEE transactions on electron devices, 2008, Vol.55 (1), p.186-196

KAWA, Jamil

2008

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An RTL-to-GDSII Flow for Single Flux Quantum Circuits Based on an Industrial EDA Toolchain

IEEE transactions on applied superconductivity, 2023-08, Vol.33 (5), p.1-8

2023

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A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond

2024 25th International Symposium on Quality Electronic Design (ISQED), 2024, p.1-8

2024

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Majority-based Design Flow for AQFP Superconducting Family

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.34-39

2022

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Low Power and Power Management for CMOS-An EDA Perspective

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.186-196

Kawa, J.

2008

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Challenges in Design and Modeling of Cold CMOS HPC Technology

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, p.107-110

2021

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Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.378-391

2010

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Power-performance-area engineering of 5nm nanowire library cells

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, p.433-436

2015

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Managing on-chip inductive effects

IEEE transactions on very large scale integration (VLSI) systems, 2002-12, Vol.10 (6), p.789-798

2002

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Modeling and analysis of differential signaling for minimizing inductive cross-talk

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.804-809

2001

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Accurate modeling of substrate resistive coupling for floating substrates

ACM transactions on design automation of electronic systems, 2006-01, Vol.11 (1), p.44-51

2006

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H-Tree Clock Synthesis in RSFQ Circuits

2020 17th Biennial Baltic Electronics Conference (BEC), 2020, p.1-5

2020

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Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics

2019 IEEE International Superconductive Electronics Conference (ISEC), 2019, p.1-3

2019

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Circuit effects in static timing

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA, 2002

Kawa, Jamil

2002

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EDA Challenges in Nano-scale Technology

IEEE Custom Integrated Circuits Conference 2006, 2006, p.845-851

2006

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Timing implications of fill metal generation methods for system-level nano-scale designs

2008 51st Midwest Symposium on Circuits and Systems, 2008, p.93-96

2008

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Automated design of tunable impedance matching networks for reconfigurable wireless applications

2008 45th ACM/IEEE Design Automation Conference, 2008, p.498-503

2008

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Interconnect Routing for Large-Scale RSFQ Circuits

A full-custom design flow and a top-down RTL-to-GDS flow for adiabatic quantum-flux-parametron logic using a commercial EDA design suite

Challenges and the status of superconducting single flux quantum technology

Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits

Repeater Insertion in SFQ Interconnect

Splitter Trees in Single Flux Quantum Circuits

Josephson Junction Stuck-At Fault Detection in SFQ Circuits

Observations in Use of a Tunnel Junction Model in Simulations of Josephson Digital Circuits

Low Power and Power Management for CMOS : An EDA Perspective : Device technologies and circuit techniques for power management

An RTL-to-GDSII Flow for Single Flux Quantum Circuits Based on an Industrial EDA Toolchain

A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond

Majority-based Design Flow for AQFP Superconducting Family

Low Power and Power Management for CMOS-An EDA Perspective

Challenges in Design and Modeling of Cold CMOS HPC Technology

Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology

Power-performance-area engineering of 5nm nanowire library cells

Managing on-chip inductive effects

Modeling and analysis of differential signaling for minimizing inductive cross-talk

Accurate modeling of substrate resistive coupling for floating substrates

H-Tree Clock Synthesis in RSFQ Circuits

Progress Toward VLSI-Capable EDA Tools for Superconductive Digital Electronics

Circuit effects in static timing

EDA Challenges in Nano-scale Technology

Timing implications of fill metal generation methods for system-level nano-scale designs

Automated design of tunable impedance matching networks for reconfigurable wireless applications

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