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Analysis of TID Process, Geometry, and Bias Condition Dependence in 14-nm FinFETs and Implications for RF and SRAM Performance

IEEE transactions on nuclear science, 2017-01, Vol.64 (1), p.285-292

2017

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Empirical Modeling of FinFET SEU Cross Sections Across Supply Voltage

IEEE transactions on nuclear science, 2019-07, Vol.66 (7), p.1427-1432

2019

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An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

IEEE transactions on nuclear science, 2016-12, Vol.63 (6), p.3003-3009

2016

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Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

IEEE transactions on nuclear science, 2018-01, Vol.65 (1), p.362-368

2018

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On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2748-2755

2012

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Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4399-4404

2013

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Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.2613-2619

2015

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Impact of Process Variations on SRAM Single Event Upsets

IEEE transactions on nuclear science, 2011-06, Vol.58 (3), p.834-839

2011

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Effect of Negative Bias Temperature Instability on the Single Event Upset Response of 40 nm Flip-Flops

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2651-2657

2012

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Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4498-4504

2013

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Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2867-2871

2012

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RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.3060-3066

2011

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Efficient Method for Estimating the Characteristics of Radiation-Induced Current Transients

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2704-2709

2012

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Single-Event Latchup in a 7-nm Bulk FinFET Technology

IEEE transactions on nuclear science, 2021-05, Vol.68 (5), p.830-834

2021

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Mitigating Total-Ionizing-Dose-Induced Threshold-Voltage Shifts Using Back-Gate Biasing in 22-nm FD-SOI Transistors

IEEE transactions on nuclear science, 2022-03, Vol.69 (3), p.374-380

2022

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Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

IEEE transactions on nuclear science, 2020-06, Vol.67 (6), p.1144-1151

2020

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A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit

IEEE transactions on nuclear science, 2009-12, Vol.56 (6), p.3152-3157

2009

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In Situ Measurement of TID-Induced Leakage Using On-Chip Frequency Modulation

IEEE transactions on nuclear science, 2022-03, Vol.69 (3), p.367-373

2022

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Estimating Single-Event Logic Cross Sections in Advanced Technologies

IEEE transactions on nuclear science, 2017-08, Vol.64 (8), p.2115-2121

2017

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An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies

IEEE transactions on nuclear science, 2018-01, Vol.65 (1), p.304-310

2018

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Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

IEEE transactions on nuclear science, 2018-08, Vol.65 (8), p.1807-1813

2018

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Effects of Total-Ionizing-Dose Irradiation on Single-Event Response for Flip-Flop Designs at a 14-/16-nm Bulk FinFET Technology Node

IEEE transactions on nuclear science, 2018-08, Vol.65 (8), p.1928-1934

2018

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A Bias-Dependent Single-Event-Enabled Compact Model for Bulk FinFET Technologies

IEEE transactions on nuclear science, 2019-03, Vol.66 (3), p.635-642

2019

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Dual-Interlocked Logic for Single-Event Transient Mitigation

IEEE transactions on nuclear science, 2018-08, Vol.65 (8), p.1872-1878

2018

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Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology

IEEE transactions on nuclear science, 2018-01, Vol.65 (1), p.413-417

2018

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Analysis of TID Process, Geometry, and Bias Condition Dependence in 14-nm FinFETs and Implications for RF and SRAM Performance

Empirical Modeling of FinFET SEU Cross Sections Across Supply Voltage

An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Impact of Process Variations on SRAM Single Event Upsets

Effect of Negative Bias Temperature Instability on the Single Event Upset Response of 40 nm Flip-Flops

Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation

Efficient Method for Estimating the Characteristics of Radiation-Induced Current Transients

Single-Event Latchup in a 7-nm Bulk FinFET Technology

Mitigating Total-Ionizing-Dose-Induced Threshold-Voltage Shifts Using Back-Gate Biasing in 22-nm FD-SOI Transistors

Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit

In Situ Measurement of TID-Induced Leakage Using On-Chip Frequency Modulation

Estimating Single-Event Logic Cross Sections in Advanced Technologies

An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies

Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation

Effects of Total-Ionizing-Dose Irradiation on Single-Event Response for Flip-Flop Designs at a 14-/16-nm Bulk FinFET Technology Node

A Bias-Dependent Single-Event-Enabled Compact Model for Bulk FinFET Technologies

Dual-Interlocked Logic for Single-Event Transient Mitigation

Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology

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