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High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch

AIP advances, 2022-03, Vol.12 (3), p.035152-035152-5

2022

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72 nm Pitch Hexagonal MTJ Array on DRAM Platform for High-Density MRAM

IEEE transactions on magnetics, 2021-11, Vol.57 (11), p.1-6

2021

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On the Understanding and Modeling of Non-Negligible Subthreshold-State Degradation (SSD) in Sub-20-nm DRAM Technology

IEEE electron device letters, 2024-09, Vol.45 (9), p.1582-1585

2024

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Enhanced TDDB-Reliability of Ultra-Thin Zirconia Capacitors Featuring Al-Doped Oxide Layers

IEEE electron device letters, 2024-06, Vol.45 (6), p.1004-1007

2024

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Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition

IEEE transactions on electron devices, 2022-12, Vol.69 (12), p.6669-6675

2022

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Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node-Part I: Defect-Based Statistical Compact Model

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.4462-4468

2024

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Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node-Part II: PBTI Aging and Optimization

IEEE transactions on electron devices, 2024-08, Vol.71 (8), p.4469-4475

2024

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Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation

2023 IEEE International Reliability Physics Symposium (IRPS), 2023, p.1-10

2023

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A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-4

2021

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Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-4

2021

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Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-3

2021

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Pitch Device Design in 10nm-Class DRAM Process through DTCO

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-4

2021

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Sub-20-nm DRAM Technology under Negative Bias Temperature Instability (NBTI): from Characterization to Physical Origin Identification

2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.9B.2-1-9B.2-7

2024

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Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM

2021 IEEE 14th International Conference on ASIC (ASICON), 2021, p.1-4

2021

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Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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Improved Model for ESD Failure Caused by Stressing No Connect Pin

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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Normalized mutual integral difference method to extract threshold voltage of MOSFETs

IEEE electron device letters, 2002-07, Vol.23 (7), p.428-430

2002

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A novel speed-up coding method in quadruple-level-cell 3D NAND flash memory

2016 5th International Symposium on Next-Generation Electronics (ISNE), 2016, p.1-2

2016

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A high speed low power negative sensing architecture for 3D NAND Flash memory

2016 China Semiconductor Technology International Conference (CSTIC), 2016, p.1-3

2016

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An Improved Area-efficient Transient ESD Power Clamp

2022 International EOS/ESD Symposium on Design and System (IEDS), 2022, p.1-4

2022

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Symmetry realization of BSIM model with dynamic reference method for circuit simulation

60th DRC. Conference Digest Device Research Conference, 2002, p.65-66

2002

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A DTCO approach on DRAM bit line capacitance and sensing margin improvement

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020, p.1-3

2020

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A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM), 2021, p.171-174

2021

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Ultra-Fast Oxide Traps in Sub-20-nm DRAM Technology: from Characterization to Physical origin identification

2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2024, p.1-3

2024

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Saddle Fin Structure Effects on the DRAM Access Transistor Performance

2021 IEEE 4th International Conference on Electronics Technology (ICET), 2021, p.50-53

2021

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High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch

72 nm Pitch Hexagonal MTJ Array on DRAM Platform for High-Density MRAM

On the Understanding and Modeling of Non-Negligible Subthreshold-State Degradation (SSD) in Sub-20-nm DRAM Technology

Enhanced TDDB-Reliability of Ultra-Thin Zirconia Capacitors Featuring Al-Doped Oxide Layers

Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition

Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node-Part I: Defect-Based Statistical Compact Model

Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node-Part II: PBTI Aging and Optimization

Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation

A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface

Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector

Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM

Pitch Device Design in 10nm-Class DRAM Process through DTCO

Sub-20-nm DRAM Technology under Negative Bias Temperature Instability (NBTI): from Characterization to Physical Origin Identification

Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM

Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation

Improved Model for ESD Failure Caused by Stressing No Connect Pin

Normalized mutual integral difference method to extract threshold voltage of MOSFETs

A novel speed-up coding method in quadruple-level-cell 3D NAND flash memory

A high speed low power negative sensing architecture for 3D NAND Flash memory

An Improved Area-efficient Transient ESD Power Clamp

Symmetry realization of BSIM model with dynamic reference method for circuit simulation

A DTCO approach on DRAM bit line capacitance and sensing margin improvement

A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align

Ultra-Fast Oxide Traps in Sub-20-nm DRAM Technology: from Characterization to Physical origin identification

Saddle Fin Structure Effects on the DRAM Access Transistor Performance

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