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FASTHash: FPGA-Based High Throughput Parallel Hash Table

High Performance Computing, 2020, Vol.12151, p.3-22

2020

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FPGA Acceleration of Number Theoretic Transform

High Performance Computing, 2021, Vol.12728, p.98-117

2021

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The KR-Benes network: a control-optimal rearrangeable permutation network

IEEE transactions on computers, 2005-05, Vol.54 (5), p.534-544

Rajgopal Kannan, Rajgopal Kannan

2005

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CASPaR: Congestion avoidance shortest path routing for delay tolerant networks

International journal of distributed sensor networks, 2017-11, Vol.13 (11), p.155014771774126

2017

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Approximating Congestion + Dilation in Networks via "Quality of Routing" Games

IEEE transactions on computers, 2012-09, Vol.61 (9), p.1270-1283

2012

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Building HVAC Scheduling Using Reinforcement Learning via Neural Network Based Model Approximation

Proceedings of the 6th ACM International Conference on Systems for Energy-Efficient Buildings, Cities, and Transportation, 2019, p.287-296

2019

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VisionAGILE: A Versatile Domain-Specific Accelerator for Computer Vision Tasks

IEEE transactions on parallel and distributed systems, 2024-12, Vol.35 (12), p.2405-2422

2024

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HitGraph: High-throughput Graph Processing Framework on FPGA

IEEE transactions on parallel and distributed systems, 2019-10, Vol.30 (10), p.2249-2264

2019

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Adaptive Routing Strategies in IEEE 802.16 Multi-Hop Wireless Backhaul Networks Based On Evolutionary Game Theory

IEEE journal on selected areas in communications, 2008-09, Vol.26 (7), p.1218-1225

2008

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PPOAccel: A High-Throughput Acceleration Framework for Proximal Policy Optimization

IEEE transactions on parallel and distributed systems, 2022-09, Vol.33 (9), p.2066-2078

2022

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Game Theory for Networks: 2nd International ICST Conference, GameNets 2011, Shanghai, China, April 11-18, 2011, Revised Selected Papers

2012 edition., 2012

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Accelerating large scale real-time GNN inference using channel pruning

Proceedings of the VLDB Endowment, 2021-05, Vol.14 (9), p.1597-1605

2021

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Accelerating Stochastic Gradient Descent Based Matrix Factorization on FPGA

IEEE transactions on parallel and distributed systems, 2020-08, Vol.31 (8), p.1897-1911

2020

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Accurate, efficient and scalable training of Graph Neural Networks

Journal of parallel and distributed computing, 2021-01, Vol.147, p.166-183

2021

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Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU

2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2023, p.23-33

2023

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Planting trees for scalable and efficient canonical hub labeling

Proceedings of the VLDB Endowment, 2019-12, Vol.13 (4), p.492-505

2019

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Parallel Peeling of Bipartite Networks for Hierarchical Dense Subgraph Discovery

ACM transactions on parallel computing, 2023-06, Vol.10 (2), p.1-35, Article 5

2023

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Learning Sparse Feature Representations Using Probabilistic Quadtrees and Deep Belief Nets

Neural processing letters, 2017-06, Vol.45 (3), p.855-867

2017

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Accelerating Allreduce With In-Network Reduction on Intel PIUMA

IEEE MICRO, 2022-03, Vol.42 (2), p.44-52

2022

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Label Efficient Regularization and Propagation for Graph Node Classification

IEEE transactions on pattern analysis and machine intelligence, 2023-12, Vol.45 (12), p.1-16

2023

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Receipt: refine coarse-grained independent tasks for parallel tip decomposition of bipartite graphs

Proceedings of the VLDB Endowment, 2020-11, Vol.14 (3), p.404-417

2020

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GPOP: A Scalable Cache- and Memory-efficient Framework for Graph Processing over Parts

ACM transactions on parallel computing, 2020-03, Vol.7 (1), p.1-24

2020

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HTNet: Dynamic WLAN Performance Prediction using Heterogenous Temporal GNN

IEEE INFOCOM 2023 - IEEE Conference on Computer Communications, 2023, p.1-10

2023

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How to Avoid Zero-Spacing in Fractionally-Strided Convolution? A Hardware-Algorithm Co-Design Methodology

2021 IEEE 28th International Conference on High Performance Computing, Data, and Analytics (HiPC), 2021, p.81-90

2021

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Optimal Discrete Net-Load Balancing in Smart Grids with High PV Penetration

ACM transactions on sensor networks, 2018-11, Vol.14 (3-4), p.1-30

2018

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FASTHash: FPGA-Based High Throughput Parallel Hash Table

FPGA Acceleration of Number Theoretic Transform

The KR-Benes network: a control-optimal rearrangeable permutation network

CASPaR: Congestion avoidance shortest path routing for delay tolerant networks

Approximating Congestion + Dilation in Networks via "Quality of Routing" Games

Building HVAC Scheduling Using Reinforcement Learning via Neural Network Based Model Approximation

VisionAGILE: A Versatile Domain-Specific Accelerator for Computer Vision Tasks

HitGraph: High-throughput Graph Processing Framework on FPGA

Adaptive Routing Strategies in IEEE 802.16 Multi-Hop Wireless Backhaul Networks Based On Evolutionary Game Theory

PPOAccel: A High-Throughput Acceleration Framework for Proximal Policy Optimization

Game Theory for Networks: 2nd International ICST Conference, GameNets 2011, Shanghai, China, April 11-18, 2011, Revised Selected Papers

Accelerating large scale real-time GNN inference using channel pruning

Accelerating Stochastic Gradient Descent Based Matrix Factorization on FPGA

Accurate, efficient and scalable training of Graph Neural Networks

Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU

Planting trees for scalable and efficient canonical hub labeling

Parallel Peeling of Bipartite Networks for Hierarchical Dense Subgraph Discovery

Learning Sparse Feature Representations Using Probabilistic Quadtrees and Deep Belief Nets

Accelerating Allreduce With In-Network Reduction on Intel PIUMA

Label Efficient Regularization and Propagation for Graph Node Classification

Receipt: refine coarse-grained independent tasks for parallel tip decomposition of bipartite graphs

GPOP: A Scalable Cache- and Memory-efficient Framework for Graph Processing over Parts

HTNet: Dynamic WLAN Performance Prediction using Heterogenous Temporal GNN

How to Avoid Zero-Spacing in Fractionally-Strided Convolution? A Hardware-Algorithm Co-Design Methodology

Optimal Discrete Net-Load Balancing in Smart Grids with High PV Penetration

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