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Accuracy-configurable adder for approximate arithmetic designs

DAC Design Automation Conference 2012, 2012, p.820-825

2012

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Configurable anti-ambipolar photoresponses for optoelectronic multi-valued logic gates

Applied physics letters, 2024-07, Vol.125 (5)

2024

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Compact Topology-Aware Bus Routing for Design Regularity

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-08, Vol.39 (8), p.1744-1749

2020

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Enhancing the Efficiency of Energy-Constrained DVFS Designs

IEEE transactions on very large scale integration (VLSI) systems, 2013-10, Vol.21 (10), p.1769-1782

2013

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Proactive Scenario Characteristic-aware Online Power Management on Mobile Systems

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Recovery-driven design: a power minimization methodology for error-tolerant processor modules

Design Automation Conference, 2010, p.825-830

2010

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Many-Core Token-Based Adaptive Power Gating

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-08, Vol.32 (8), p.1288-1292

2013

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Fluctuation-Based Fade Detection for Local Scene Changes

IEEE access, 2021, Vol.9, p.149732-149743

2021

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Self-selective ferroelectric memory realized with semimetalic graphene channel

NPJ 2D materials and applications, 2021-12, Vol.5 (1), p.1-9, Article 90

2021

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SmartGrid: Video Retargeting With Spatiotemporal Grid Optimization

IEEE access, 2019, Vol.7, p.127564-127579

2019

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FPGA Controller Design for High-Frequency LLC Resonant Converters

IEEJ JOURNAL OF INDUSTRY APPLICATIONS, 2020-09, Vol.9 (5), p.523-529

2020

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Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems

IEEE access, 2019, Vol.7, p.95305-95313

2019

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Statistical Leakage Analysis Using Gaussian Mixture Model

IEEE access, 2018-01, Vol.6, p.51939-51950

2018

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A Novel Ternary Multiplier Based on Ternary CMOS Compact Model

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 2017, p.25-30

2017

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SoftCorner: Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems

IEEE access, 2018, Vol.6, p.60115-60127

2018

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Mobile Transformer Accelerator Exploiting Various Line Sparsity and Tile-Based Dynamic Quantization

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-06, Vol.43 (6), p.1808-1821

2024

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Fast predictive useful skew methodology for timing-driven placement optimization

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-03, Vol.31 (3), p.404-417

2012

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Designing a processor from the ground up to allow voltage/reliability tradeoffs

HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, 2010, p.1-11

2010

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Statistical analysis and modeling for error composition in approximate computation circuits

2013 IEEE 31st International Conference on Computer Design (ICCD), 2013, p.47-53

2013

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Sensitivity-guided metaheuristics for accurate discrete gate sizing

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012, p.233-239

2012

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CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping

2022 IEEE 40th International Conference on Computer Design (ICCD), 2022, p.336-343

2022

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MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors

IEEE transactions on circuits and systems. I, Regular papers, 2024-05, Vol.71 (5), p.2045-2056

2024

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A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2020-09, Vol.67 (9), p.3138-3151

2020

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Low-Power Ternary Multiplication Using Approximate Computing

IEEE transactions on circuits and systems. II, Express briefs, 2021-08, Vol.68 (8), p.2947-2951

2021

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Accuracy-configurable adder for approximate arithmetic designs

Configurable anti-ambipolar photoresponses for optoelectronic multi-valued logic gates

Compact Topology-Aware Bus Routing for Design Regularity

Enhancing the Efficiency of Energy-Constrained DVFS Designs

Proactive Scenario Characteristic-aware Online Power Management on Mobile Systems

Recovery-driven design: a power minimization methodology for error-tolerant processor modules

Many-Core Token-Based Adaptive Power Gating

Fluctuation-Based Fade Detection for Local Scene Changes

Self-selective ferroelectric memory realized with semimetalic graphene channel

SmartGrid: Video Retargeting With Spatiotemporal Grid Optimization

FPGA Controller Design for High-Frequency LLC Resonant Converters

Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems

Statistical Leakage Analysis Using Gaussian Mixture Model

A Novel Ternary Multiplier Based on Ternary CMOS Compact Model

SoftCorner: Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems

Mobile Transformer Accelerator Exploiting Various Line Sparsity and Tile-Based Dynamic Quantization

Fast predictive useful skew methodology for timing-driven placement optimization

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

Designing a processor from the ground up to allow voltage/reliability tradeoffs

Statistical analysis and modeling for error composition in approximate computation circuits

Sensitivity-guided metaheuristics for accurate discrete gate sizing

CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping

MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

Low-Power Ternary Multiplication Using Approximate Computing

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