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A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.210-218

2007

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A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

IEEE journal of solid-state circuits, 2007, Vol.42 (1), p.210-218

2007

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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.282-613

2008

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A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.40-512 Vol.1

2004

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A 0.18μm 3.0V 64Mb non-volatile phase-transition random-access memory (PRAM)

First edition, 2004

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A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1436-1445

1999

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A 0.25-mu m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1436-1445

1999

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A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1436-1445

1999

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A 0.617-2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode

Sensors (Basel, Switzerland), 2022-03, Vol.22 (6), p.2276

2022

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1,1,1 - 삼염화에탄의 합성공정개발

화학공학, 1976-06, Vol.14 (3), p.169

1976

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1 , 1 , 2 - 삼염화에탄의 기상 염소화 반응

화학공학, 1977-10, Vol.15 (5), p.343

1977

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A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012, p.637-640

2012

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A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.314-496 vol.1

2003

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A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.300-494 vol.1

2003

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A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1943-1951

2003

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012, Vol.47 (1), p.107-116

2012

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.107-116

2012

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A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.250-260

2017

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A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.168-177

2013

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A 1.248–2.918 Gb/s low-power transmitter for MIPI M-PHY with 2-step impedance calibration loop in 0.11 μm CMOS

Analog integrated circuits and signal processing, 2015-05, Vol.83 (2), p.129-142

2015

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A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking

2011 IEEE International Solid-State Circuits Conference, 2011, p.496-498

2011

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A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

2012 IEEE International Solid-State Circuits Conference, 2012, p.38-40

2012

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A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13(3), 51, pp.185-192

2013

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A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

Journal of semiconductor technology and science, 2013, Vol.13 (3), p.185-192

2013

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A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.140-141,141a

2009

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A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 0.1-μm 1.8-V 256-Mb phase-change random access memory (PRAM) with 66-MHz synchronous burst-read operation

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

A 0.18μm 3.0V 64Mb non-volatile phase-transition random-access memory (PRAM)

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.25-mu m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.617-2.7 GHz Highly Linear High-Power Dual Port 15 Throws Antenna Switch Module (DP15T-ASM) with Branched-Antenna Technique and Termination Mode

1,1,1 - 삼염화에탄의 합성공정개발

1 , 1 , 2 - 삼염화에탄의 기상 염소화 반응

A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer

A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

A 1.248–2.918 Gb/s low-power transmitter for MIPI M-PHY with 2-step impedance calibration loop in 0.11 μm CMOS

A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

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