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Prediction of data retention time distribution of DRAM by physics-based statistical Simulation

IEEE transactions on electron devices, 2005-11, Vol.52 (11), p.2422-2429

2005

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A New Direct Evaluation Method to Obtain the Data Retention Time Distribution of DRAM

IEEE transactions on electron devices, 2006-09, Vol.53 (9), p.2344-2350

2006

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The Simulation of the Dynamic Characteristics of Friction Stir Welding and the Structural Deflection of Base Materials

Applied sciences, 2022-10, Vol.12 (19), p.9847

2022

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Modeling alpha-particle-induced accelerated soft error rate in semiconductor memory

IEEE transactions on electron devices, 2003-07, Vol.50 (7), p.1652-1657

2003

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Abnormal junction leakage characteristics in titanium-capped cobalt disilicide

Journal of applied physics, 1999-11, Vol.86 (9), p.5293-5295

1999

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Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain N-channel metal-oxide-semiconductor field effect transistors

Japanese Journal of Applied Physics, 1994, Vol.33 (1B), p.606-611

1994

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Trap evaluations of metal/oxide/silicon field-effect transistors with high- k gate dielectric using charge pumping method

Applied physics letters, 2002-09, Vol.81 (11), p.2050-2052

2002

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Reduction of Reverse Short-Channel Effect in High-Energy Implanted Retrograde Well

Journal of the Korean Physical Society, 2002-04, Vol.40 (4), p.649

2002

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Impact of Nitrogen Implantation in Lightly Doped Drain (NIL) on Deep Sub-Micron CMOS Devices

Japanese Journal of Applied Physics, 2000, Vol.39 (4S), p.2141-2146

2000

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Characteristics of n+–p junction leakage induced by tantalum pentoxide gate insulator and gate reoxidation

Applied physics letters, 2001-05, Vol.78 (21), p.3244-3246

2001

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Analysis of body bias effect with PD-SOI for analog and RF applications

Solid-state electronics, 2002-08, Vol.46 (8), p.1169-1176

2002

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Effects of nitrogen implantation in silicon for shallow p+-n junction formation

Applied physics letters, 1999-03, Vol.74 (13), p.1833-1835

1999

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Effects of Shallow Trench Isolation on Silicon-on-Insulator Devices for Mixed Signal Processing

Journal of the Korean Physical Society, 2002, 40(4), , pp.653-657

2002

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A simple voltage scaling formula for low-power CMOS circuits

IEEE transactions on electron devices, 1999-04, Vol.46 (4), p.803-805

1999

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Current-crowding effect in diagonal MOSFET's

IEEE electron device letters, 1993-06, Vol.14 (6), p.289-291

1993

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Ultra thin-oxide damage from gate charging during PETEOS deposition processing

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999, p.245-248

1999

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Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), 1998, p.287-290

1998

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Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999, p.41-44

1999

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An anomalous device degradation of SOI devices with STI

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125), 2000, p.132-133

2000

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Performance improvements in high-density DRAM application using 0.15 /spl mu/m body-contacted SOI technology

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125), 2000, p.76-77

2000

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Consistent Sampling Approximations in Abstract Hilbert Spaces

Axioms, 2024-07, Vol.13 (7), p.489

2024

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Modeling of retention time distribution of DRAM cell using a Monte-Carlo method

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, 2004, p.399-402

2004

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Accurate evaluation of gate delay for low-power and high-density 0.18 /spl mu/m CMOSFET technology

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361), 1999, p.427-429

1999

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Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parameters

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999, p.905-908

1999

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A novel NMOS transistor for high performance ESD protection devices in 0.18 /spl mu/m CMOS technology utilizing salicide process

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476), 2000, p.407-412

2000

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Prediction of data retention time distribution of DRAM by physics-based statistical Simulation

A New Direct Evaluation Method to Obtain the Data Retention Time Distribution of DRAM

The Simulation of the Dynamic Characteristics of Friction Stir Welding and the Structural Deflection of Base Materials

Modeling alpha-particle-induced accelerated soft error rate in semiconductor memory

Abnormal junction leakage characteristics in titanium-capped cobalt disilicide

Physical analysis for saturation behavior of hot-carrier degradation in lightly doped drain N-channel metal-oxide-semiconductor field effect transistors

Trap evaluations of metal/oxide/silicon field-effect transistors with high- k gate dielectric using charge pumping method

Reduction of Reverse Short-Channel Effect in High-Energy Implanted Retrograde Well

Impact of Nitrogen Implantation in Lightly Doped Drain (NIL) on Deep Sub-Micron CMOS Devices

Characteristics of n+–p junction leakage induced by tantalum pentoxide gate insulator and gate reoxidation

Analysis of body bias effect with PD-SOI for analog and RF applications

Effects of nitrogen implantation in silicon for shallow p+-n junction formation

Effects of Shallow Trench Isolation on Silicon-on-Insulator Devices for Mixed Signal Processing

A simple voltage scaling formula for low-power CMOS circuits

Current-crowding effect in diagonal MOSFET's

Ultra thin-oxide damage from gate charging during PETEOS deposition processing

Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging

Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits

An anomalous device degradation of SOI devices with STI

Performance improvements in high-density DRAM application using 0.15 /spl mu/m body-contacted SOI technology

Consistent Sampling Approximations in Abstract Hilbert Spaces

Modeling of retention time distribution of DRAM cell using a Monte-Carlo method

Accurate evaluation of gate delay for low-power and high-density 0.18 /spl mu/m CMOSFET technology

Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parameters

A novel NMOS transistor for high performance ESD protection devices in 0.18 /spl mu/m CMOS technology utilizing salicide process

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