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Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1469-1480

2011

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At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

IEEE transactions on computers, 2014-03, Vol.63 (3), p.703-717

2014

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Robust Near-Threshold Design With Fine-Grained Performance Tunability

IEEE transactions on circuits and systems. I, Regular papers, 2012-08, Vol.59 (8), p.1815-1825

2012

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Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators

IEEE transactions on computers, 2015-08, Vol.64 (8), p.2132-2144

2015

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Thermally-aware sensor allocation for real-time monitoring and mitigation of FEOL aging in System-on-Chip (SoC) applications

2017 IEEE International Reliability Physics Symposium (IRPS), 2017, p.4C-6.1-4C-6.5

2017

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Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters

IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.927-931

2012

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Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits

IEEE journal on emerging and selected topics in circuits and systems, 2011-06, Vol.1 (2), p.131-140

2011

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A resilient architecture for low latency communication in shared-L1 processor clusters

Proceedings of the Conference on Design, Automation and Test in Europe, 2012, p.887-892

2012

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A resilient architecture for low latency communication in shared-L1 processor clusters

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.887-892

2012

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A floorplan-aware interactive tool flow for NoC design and synthesis

2009 IEEE International SOC Conference (SOCC), 2009, p.379-382

2009

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Reliable network-on-chip based on generalized de Bruijn graph

2007 IEEE International High Level Design Validation and Test Workshop, 2007, p.3-10

2007

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Automatic synthesis of near-threshold circuits with fine-grained performance tunability

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010, p.401-406

2010

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A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007, p.1-4

2007

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Graph based test case generation for TLM functional verification

Microprocessors and microsystems, 2008-08, Vol.32 (5), p.288-295

2008

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A distributed and topology-agnostic approach for on-line NoC testing

Proceedings of the Fifth ACM/IEEE International Symposium, 2011, p.113-120

2011

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Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors

2007 IEEE/ACS International Conference on Computer Systems and Applications, 2007, p.528-534

2007

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De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs

2008 Design, Automation and Test in Europe, 2008, p.1370-1373

2008

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A New Approach for Design and Verification of Transaction Level Models

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.3760-3763

2007

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Row-based FBB: A design-time optimization for post-silicon tunable circuits

Microelectronics, 2012-07, Vol.43 (7), p.456-465

2012

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A shared-FPU architecture for ultra-low power MPSoCs

Proceedings of the ACM International Conference on Computing Frontiers, 2013, p.1-8

2013

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A new physical routing approach for robust bundled signaling on NoC links

Proceedings of the 20th symposium on Great lakes symposium on VLSI, 2010, p.3-8

2010

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A multi-banked shared-l1 cache architecture for tightly coupled processor clusters

2012 International Symposium on System on Chip (SoC), 2012, p.1-5

2012

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A tightly-coupled multi-core cluster with shared-memory HW accelerators

2012 International Conference on Embedded Computer Systems (SAMOS), 2012, p.96-103

2012

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Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.714-720

2008

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COMRA: An efficient low-energy core mapping and routing path allocation algorithm for heterogeneous NoCs

2009 4th International Design and Test Workshop (IDT), 2009, p.1-6

2009

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Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph

At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs

Robust Near-Threshold Design With Fine-Grained Performance Tunability

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators

Thermally-aware sensor allocation for real-time monitoring and mitigation of FEOL aging in System-on-Chip (SoC) applications

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters

Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits

A resilient architecture for low latency communication in shared-L1 processor clusters

A resilient architecture for low latency communication in shared-L1 processor clusters

A floorplan-aware interactive tool flow for NoC design and synthesis

Reliable network-on-chip based on generalized de Bruijn graph

Automatic synthesis of near-threshold circuits with fine-grained performance tunability

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services

Graph based test case generation for TLM functional verification

A distributed and topology-agnostic approach for on-line NoC testing

Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors

De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs

A New Approach for Design and Verification of Transaction Level Models

Row-based FBB: A design-time optimization for post-silicon tunable circuits

A shared-FPU architecture for ultra-low power MPSoCs

A new physical routing approach for robust bundled signaling on NoC links

A multi-banked shared-l1 cache architecture for tightly coupled processor clusters

A tightly-coupled multi-core cluster with shared-memory HW accelerators

Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification

COMRA: An efficient low-energy core mapping and routing path allocation algorithm for heterogeneous NoCs

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