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One-Transistor Poly-Si Memory Devices With Near-Zero Subthreshold Swing and Extended Retention Time

IEEE electron device letters, 2024-06, Vol.45 (6), p.1008-1011

Kuo, Po-Yi

2024

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Heterogeneous Integration of Atomically‐Thin Indium Tungsten Oxide Transistors for Low‐Power 3D Monolithic Complementary Inverter

Advanced science, 2023-03, Vol.10 (9), p.e2205481-n/a

2023

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Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

IEEE transactions on electron devices, 2020-02, Vol.67 (2), p.711-716

2020

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Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

Scientific reports, 2019-05, Vol.9 (1), p.7579-7579, Article 7579

2019

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Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

IEEE electron device letters, 2019-11, Vol.40 (11), p.1708-1711

2019

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High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n+-Doped Poly-Si NWs Channels Junctionless FETs

IEEE transactions on electron devices, 2014-11, Vol.61 (11), p.3821-3826

2014

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Mobility enhancement for high stability tungsten-doped indium-zinc oxide thin film transistors with a channel passivation layer

RSC advances, 2018-01, Vol.8 (13), p.6925-693

2018

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Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2992-2998

2017

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High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

IEEE transactions on electron devices, 2016-11, Vol.63 (11), p.4179-4184

2016

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Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application

IEEE transactions on electron devices, 2016-12, Vol.63 (12), p.4998-5003

2016

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Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs

IEEE transactions on nanotechnology, 2020, Vol.19, p.322-327

2020

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An efficient simulation optimization method for the generalized redundancy allocation problem

European journal of operational research, 2018-03, Vol.265 (3), p.1094-1101

2018

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Numerical Analysis of Oxygen-Related Defects in Amorphous In-W-O Nanosheet Thin-Film Transistor

Nanomaterials (Basel, Switzerland), 2021-11, Vol.11 (11), p.3070

2021

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Asymmetric Low Metal Contamination Ni-Induced Lateral Crystallization Polycrystalline-Silicon Thin-Film Transistors With Low OFF-State Currents for Back-End of Line (BEOL) Compatible Devices Applications

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.1317-1322

2020

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Extraction Method for Equivalent Oxide Thickness of a Thin High-κ Gate Insulator and Estimation of Field-Effect Mobility in Amorphous Oxide Semiconductor Nano-Sheet Junctionless Transistors

IEEE transactions on electron devices, 2022-09, Vol.69 (9), p.4791-4795

2022

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Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs

IEEE journal of the Electron Devices Society, 2018-01, Vol.6, p.314-319

2018

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Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

IEEE electron device letters, 2011-02, Vol.32 (2), p.173-175

2011

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Investigation of low operation voltage InZnSnO thin-film transistors with different high-k gate dielectric by physical vapor deposition

Thin solid films, 2018-08, Vol.660, p.885-890

2018

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Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2160-2166

2012

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Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack

Thin solid films, 2018-08, Vol.660, p.578-584

2018

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Characteristics of Self-Aligned Si/Ge T-Gate Poly-Si Thin-Film Transistors With High on/off Current Ratio

IEEE transactions on electron devices, 2007-05, Vol.54 (5), p.1171-1176

2007

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The influence on electrical characteristics of amorphous indium tungsten oxide thin film transistors with multi-stacked active layer structure

Thin solid films, 2018-11, Vol.666, p.94-99

2018

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Performance improvements of tungsten and zinc doped indium oxide thin film transistor by fluorine based double plasma treatment with a high-K gate dielectric

Thin solid films, 2018-11, Vol.665, p.117-122

2018

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High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels

IEEE electron device letters, 2012-02, Vol.33 (2), p.215-217

2012

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Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures

IEEE transactions on electron devices, 2011-07, Vol.58 (7), p.2008-2013

2011

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One-Transistor Poly-Si Memory Devices With Near-Zero Subthreshold Swing and Extended Retention Time

Heterogeneous Integration of Atomically‐Thin Indium Tungsten Oxide Transistors for Low‐Power 3D Monolithic Complementary Inverter

Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

Two-Dimensional-Like Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Low Operation Voltage

Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n+-Doped Poly-Si NWs Channels Junctionless FETs

Mobility enhancement for high stability tungsten-doped indium-zinc oxide thin film transistors with a channel passivation layer

Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs

High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application

Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs

An efficient simulation optimization method for the generalized redundancy allocation problem

Numerical Analysis of Oxygen-Related Defects in Amorphous In-W-O Nanosheet Thin-Film Transistor

Asymmetric Low Metal Contamination Ni-Induced Lateral Crystallization Polycrystalline-Silicon Thin-Film Transistors With Low OFF-State Currents for Back-End of Line (BEOL) Compatible Devices Applications

Extraction Method for Equivalent Oxide Thickness of a Thin High-κ Gate Insulator and Estimation of Field-Effect Mobility in Amorphous Oxide Semiconductor Nano-Sheet Junctionless Transistors

Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs

Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

Investigation of low operation voltage InZnSnO thin-film transistors with different high-k gate dielectric by physical vapor deposition

Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors

Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack

Characteristics of Self-Aligned Si/Ge T-Gate Poly-Si Thin-Film Transistors With High on/off Current Ratio

The influence on electrical characteristics of amorphous indium tungsten oxide thin film transistors with multi-stacked active layer structure

Performance improvements of tungsten and zinc doped indium oxide thin film transistor by fluorine based double plasma treatment with a high-K gate dielectric

High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels

Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures

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