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A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

IEEE journal of solid-state circuits, 2008-05, Vol.43 (5), p.1195-1206

2008

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A slew-rate controlled output driver using PLL as compensation circuit

IEEE journal of solid-state circuits, 2003-07, Vol.38 (7), p.1227-1233

2003

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Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-07, Vol.54 (7), p.601-605

2007

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A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

2008 IEEE Custom Integrated Circuits Conference, 2008, p.89-92

2008

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An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface

2007 IEEE Custom Integrated Circuits Conference, 2007, p.373-376

2007

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A 100-dB gain-corrected delta-sigma audio DAC with headphone driver

Analog integrated circuits and signal processing, 2007-04, Vol.51 (1), p.27-31

2007

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A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling

2008 IEEE Custom Integrated Circuits Conference, 2008, p.165-168

2008

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A CMOS 16-bit 20MSPS analog front end for scanner/MFP applications

IEEE transactions on consumer electronics, 2003-08, Vol.49 (3), p.647-652

2003

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A 16b 10MS/s digitally self-calibrated ADC with time constant control

2008 IEEE Custom Integrated Circuits Conference, 2008, p.113-116

2008

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A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC

2007 IEEE Custom Integrated Circuits Conference, 2007, p.185-188

2007

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A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure

IEEE Custom Integrated Circuits Conference 2006, 2006, p.145-148

2006

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A new level-up shifter for high speed and wide range interface in ultra deep sub-micron

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1063-1065 Vol. 2

2005

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A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS

2008 IEEE Symposium on VLSI Circuits, 2008, p.218-219

2008

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An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing

2009 IEEE Custom Integrated Circuits Conference, 2009, p.171-174

2009

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A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2008, 8(4), 32, pp.318-325

2008

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A 3 V 6-bit 70 MSPS dual CMOS A/D converter for DBS (direct broadcasting for satellite)

IEEE transactions on consumer electronics, 1997-08, Vol.43 (3), p.863-867

1997

Volltextzugriff (PDF)

A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS

2008 IEEE Symposium on VLSI Circuits, 2008, p.176-177

2008

Volltextzugriff (PDF)

A high current driving charge pump with current regulation method

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.207-210

2005

Volltextzugriff (PDF)

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.231-234

2005

Volltextzugriff (PDF)

A 10 bit 30 MSPS CMOS A/D converter for a high performance video application system

IEEE transactions on consumer electronics, 1997-11, Vol.43 (4), p.1301-1304

1997

Volltextzugriff (PDF)

A new level shifter in ultra deep sub-micron for low to wide range voltage applications

IEEE International SOC Conference, 2004. Proceedings, 2004, p.155-156

2004

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A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

Journal of semiconductor technology and science, 2008, Vol.8 (4), p.318-325

2008

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A 2.4 V, 12 mW stereo audio D/A converter with double sampling switching

2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, Vol.1, p.447-450 vol.1

2000

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A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004, p.291-294

2004

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A DLL based 10-320 MHz clock synchronizer

2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, Vol.5, p.265-268 vol.5

2000

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A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

A slew-rate controlled output driver using PLL as compensation circuit

Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface

A 100-dB gain-corrected delta-sigma audio DAC with headphone driver

A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling

A CMOS 16-bit 20MSPS analog front end for scanner/MFP applications

A 16b 10MS/s digitally self-calibrated ADC with time constant control

A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC

A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure

A new level-up shifter for high speed and wide range interface in ultra deep sub-micron

A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing

A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

A 3 V 6-bit 70 MSPS dual CMOS A/D converter for DBS (direct broadcasting for satellite)

A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS

A high current driving charge pump with current regulation method

A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature

A 10 bit 30 MSPS CMOS A/D converter for a high performance video application system

A new level shifter in ultra deep sub-micron for low to wide range voltage applications

A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

A 2.4 V, 12 mW stereo audio D/A converter with double sampling switching

A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture

A DLL based 10-320 MHz clock synchronizer

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