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The Opportunity of Negative Capacitance Behavior in Flash Memory for High‐Density and Energy‐Efficient In‐Memory Computing Applications

Advanced functional materials, 2023-02, Vol.33 (7), p.n/a

2023

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Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS

IEEE journal of solid-state circuits, 2017-02, Vol.52 (2), p.496-504

2017

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Power-Gated 9T SRAM Cell for Low-Energy Operation

IEEE transactions on very large scale integration (VLSI) systems, 2017-03, Vol.25 (3), p.1183-1187

2017

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A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area

IEEE transactions on circuits and systems. II, Express briefs, 2017-06, Vol.64 (6), p.700-704

2017

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Current Measurement Transducer Based on Current-to-Voltage-to-Frequency Converting Ring Oscillator with Cascade Bias Circuit

Sensors (Basel, Switzerland), 2020-01, Vol.20 (2), p.493

2020

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Comparative Study of Various Latch-Type Sense Amplifiers

IEEE transactions on very large scale integration (VLSI) systems, 2014-02, Vol.22 (2), p.425-429

2014

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A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.181-186

2012

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Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

IEEE transactions on very large scale integration (VLSI) systems, 2015-11, Vol.23 (11), p.2748-2752

2015

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Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM

IEEE transactions on circuits and systems. I, Regular papers, 2014-12, Vol.61 (12), p.3376-3385

2014

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One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

IEEE transactions on circuits and systems. I, Regular papers, 2020-05, Vol.67 (5), p.1551-1561

2020

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A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

IEEE transactions on very large scale integration (VLSI) systems, 2012-11, Vol.20 (11), p.2044-2053

2012

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Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

IEEE transactions on circuits and systems. I, Regular papers, 2015-07, Vol.62 (7), p.1776-1784

2015

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Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

IEEE access, 2021, Vol.9, p.57393-57403

2021

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Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

IEEE transactions on circuits and systems. I, Regular papers, 2009-07, Vol.56 (7), p.1428-1441

2009

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All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash

IEEE access, 2021, Vol.9, p.28001-28011

2021

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STT-MRAM Sensing: A Review

IEEE transactions on circuits and systems. II, Express briefs, 2021-01, Vol.68 (1), p.12-18

2021

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High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops

IEEE access, 2021, Vol.9, p.35549-35561

2021

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Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM

IEEE transactions on circuits and systems. II, Express briefs, 2016-06, Vol.63 (6), p.578-582

2016

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Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells

IEEE access, 2021, Vol.9, p.127895-127905

2021

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SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis

IEEE transactions on circuits and systems. I, Regular papers, 2017-08, Vol.64 (8), p.2063-2072

2017

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Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation

IEEE transactions on circuits and systems. I, Regular papers, 2017-10, Vol.64 (10), p.2737-2747

2017

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A Split-Path Sensing Circuit for Spin Torque Transfer MRAM

IEEE transactions on circuits and systems. II, Express briefs, 2014-03, Vol.61 (3), p.193-197

2014

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Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector

IEEE transactions on circuits and systems. II, Express briefs, 2014-01, Vol.61 (1), p.1-5

2014

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CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution

IEEE access, 2020, Vol.8, p.187754-187765

2020

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A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

IEEE transactions on circuits and systems. II, Express briefs, 2015-12, Vol.62 (12), p.1109-1113

2015

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The Opportunity of Negative Capacitance Behavior in Flash Memory for High‐Density and Energy‐Efficient In‐Memory Computing Applications

Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS

Power-Gated 9T SRAM Cell for Low-Energy Operation

A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area

Current Measurement Transducer Based on Current-to-Voltage-to-Frequency Converting Ring Oscillator with Cascade Bias Circuit

Comparative Study of Various Latch-Type Sense Amplifiers

A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash

STT-MRAM Sensing: A Review

High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops

Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM

Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells

SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation

A Split-Path Sensing Circuit for Spin Torque Transfer MRAM

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector

CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

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