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A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces

IEEE journal of solid-state circuits, 2023-08, Vol.58 (8), p.1-12

2023

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A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2024-03, Vol.71 (3), p.1-1

2024

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A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line

IEEE journal of solid-state circuits, 2021-06, Vol.56 (6), p.1886-1896

2021

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A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.212-223

2022

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A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1890-1901

2016

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A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.1814-1818

2020

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A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs

IEEE transactions on circuits and systems. II, Express briefs, 2016-02, Vol.63 (2), p.141-145

2016

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An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface

IEEE journal of solid-state circuits, 2014-11, Vol.49 (11), p.2618-2630

2014

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13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.246-248

2024

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A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1945-1959

2015

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Reduction of Transient Far-End Crosstalk Voltage and Jitter in DIMM Connectors for DRAM Interface

IEEE microwave and wireless components letters, 2009-01, Vol.19 (1), p.15-17

2009

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A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

IEEE journal of solid-state circuits, 2012-09, Vol.47 (9), p.2068-2079

2012

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A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.2891-2900

2009

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A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2010, 10(3), 39, pp.232-239

2010

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A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

IEEE transactions on advanced packaging, 2008-11, Vol.31 (4), p.809-817

2008

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A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C184-C185

2015

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Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces

IEEE transactions on advanced packaging, 2010-05, Vol.33 (2), p.552-558

2010

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Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements

IEICE transactions on electronics, 2006-03, Vol.E89-C (3), p.410-419

LEE, H. B.

2006

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A 4Gbps 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control

2008 IEEE Asian Solid-State Circuits Conference, 2008, p.201-204

2008

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Serpentine Guard Trace to Reduce Far-end Crosstalk and Even-Odd Mode Velocity Mismatch of Microstrip Lines by More than 40

2007 Proceedings 57th Electronic Components and Technology Conference, 2007, p.329-332

2007

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A floating tap termination scheme with inverted DBI AC and floating tap forcing technique for high-speed low-power signaling

2017 Symposium on VLSI Circuits, 2017, p.C190-C191

2017

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Prostate-specific antigen density predicts favorable pathology and biochemical recurrence in patients with intermediate-risk prostate cancer

Asian journal of andrology, 2016-05, Vol.18 (3), p.480-484

2016

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A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

Journal of semiconductor technology and science, 2010, Vol.10 (3), p.232-239

2010

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A transmitter with different output timing to compensate for the crosstalk-induced jitter of coupled microstrip lines

2010 International SoC Design Conference, 2010, p.364-367

2010

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A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface

13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

Reduction of Transient Far-End Crosstalk Voltage and Jitter in DIMM Connectors for DRAM Interface

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control

A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines

A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces

Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements

A 4Gbps 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control

Serpentine Guard Trace to Reduce Far-end Crosstalk and Even-Odd Mode Velocity Mismatch of Microstrip Lines by More than 40

A floating tap termination scheme with inverted DBI AC and floating tap forcing technique for high-speed low-power signaling

Prostate-specific antigen density predicts favorable pathology and biochemical recurrence in patients with intermediate-risk prostate cancer

A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

A transmitter with different output timing to compensate for the crosstalk-induced jitter of coupled microstrip lines

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