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Simulation Study of Dominant Statistical Variability Sources in 32-nm High- \kappa/Metal Gate CMOS

IEEE electron device letters, 2012-05, Vol.33 (5), p.643-645

2012

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Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies-Part II: DC and AC Model Description

IEEE transactions on electron devices, 2015-09, Vol.62 (9), p.2760-2768

2015

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In-wafer variability in FD-SOI MOSFETs: detailed analysis and statistical modelling

Semiconductor science and technology, 2020-05, Vol.35 (5), p.55023

2020

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Modelling and analysis of gate leakage current and its wafer level variability in advanced FD-SOI MOSFETs

Solid-state electronics, 2020-01, Vol.163, p.107643, Article 107643

2020

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Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

Solid-state electronics, 2018-07, Vol.145, p.19-28

2018

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Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

IEEE transactions on electron devices, 2011-11, Vol.58 (11), p.3793-3800

2011

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Transadmittance Efficiency Under NQS Operation in Asymmetric Double Gate FDSOI MOSFET

IEEE transactions on electron devices, 2019-01, Vol.66 (1), p.300-307

2019

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Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

IEEE transactions on electron devices, 2018-01, Vol.65 (1)

2018

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Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K

Applied physics letters, 2020-06, Vol.116 (24)

2020

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Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, p.289-292

2021

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Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature

Solid-state electronics, 2021-12, Vol.186, p.108071, Article 108071

2021

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RF performances at cryogenic temperature of inductors integrated in a FDSOI technology

Solid-state electronics, 2022-08, Vol.194, p.108285, Article 108285

2022

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Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI

2017 International Conference of Microelectronic Test Structures (ICMTS), 2017, p.1-5

2017

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Test structures for interdie variations monitoring in presence of statistical random variability

2012 IEEE International Conference on Microelectronic Test Structures, 2012, p.36-42

2012

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Experimental /} Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

IEEE transactions on electron devices, 2018-01, Vol.65 (1), p.11-18

2018

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Characterization and Modeling of Gate-Induced-Drain-Leakage

IEICE transactions on electronics, 2005-05, Vol.E88-C (5), p.829-837

GILIBERT, F.

2005

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Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K

2022 IEEE International Reliability Physics Symposium (IRPS), 2022, p.7A.3-1-7A.3-6

2022

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Characterization Methodology for MOSFET Local Systematic Variability in Presence of Statistical Variability

Journal of low-power electronics, 2014-03, Vol.10 (1), p.127-136

2014

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L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technology

2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2020, p.311-314

2020

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Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications

2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS), 2020, p.1-5

2020

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Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

Solid-state electronics, 2007-11, Vol.51 (11), p.1485-1493

2007

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New physical insight for analog application in PSP bulk compact model

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2018, p.356-359

2018

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Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations

Journal of low-power electronics, 2012-02, Vol.8 (1), p.113-124

2012

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Sensitivity analysis of C-V global variability for 28 nm FD-SOI

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017, p.132-135

2017

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Direct Measurements and Modeling of Avalanche Dynamics and Quenching in SPADs

ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC), 2023, p.144-147

2023

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Simulation Study of Dominant Statistical Variability Sources in 32-nm High- \kappa/Metal Gate CMOS

Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies-Part II: DC and AC Model Description

In-wafer variability in FD-SOI MOSFETs: detailed analysis and statistical modelling

Modelling and analysis of gate leakage current and its wafer level variability in advanced FD-SOI MOSFETs

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

Transadmittance Efficiency Under NQS Operation in Asymmetric Double Gate FDSOI MOSFET

Experimental gm/ID Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K

Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET

Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature

RF performances at cryogenic temperature of inductors integrated in a FDSOI technology

Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI

Test structures for interdie variations monitoring in presence of statistical random variability

Experimental /} Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Characterization and Modeling of Gate-Induced-Drain-Leakage

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K

Characterization Methodology for MOSFET Local Systematic Variability in Presence of Statistical Variability

L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technology

Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications

Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

New physical insight for analog application in PSP bulk compact model

Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations

Sensitivity analysis of C-V global variability for 28 nm FD-SOI

Direct Measurements and Modeling of Avalanche Dynamics and Quenching in SPADs

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