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Near-threshold all-digital PLL with dynamic voltage scaling power management

Electronics letters, 2016-01, Vol.52 (2), p.109-111

2016

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High throughput concurrent lookahead adaptive decision feedback equaliser

IET circuits, devices & systems, 2012, Vol.6 (1), p.52-62

2012

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Low-error reduced-width Booth multipliers for DSP applications

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2003-11, Vol.50 (11), p.1470-1474

2003

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Design techniques for high-speed multirate multistage FIR digital filters

International journal of electronics, 2006-10, Vol.93 (10), p.699-721

2006

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Design and analysis of digital data recovery circuits using oversampling

IET circuits, devices & systems, 2007-02, Vol.1 (1), p.93-101

2007

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Low switching noise and load-adaptive output buffer design techniques

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1239-1249

2001

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Effect of chlorination bulking control on water quality and phosphate release/uptake in an anaerobic-oxic activated sludge system

Water science and technology, 2004, Vol.50 (8), p.177

2004

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A bibliometric study of semiconductor literature, 1978-1997

Scientometrics, 2000-11, Vol.49 (3), p.491-509

2000

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Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y Line

2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, p.227-230

2019

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Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07)

IEEE journal of solid-state circuits, 2008-11, Vol.43 (11), p.2352-2353

2008

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Antiplatelet Constituents of Formosan Rubia akane

Journal of natural products (Washington, D.C.), 1994-02, Vol.57 (2), p.313-316

1994

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DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2006-09, Vol.53 (9), p.827-831

2006

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Flavonol Glycosides and Cytotoxic Triterpenoids from Alphitonia Philippinensis

Journal of the Chinese Chemical Society (Taipei), 2004-08, Vol.51 (4), p.827-834

2004

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An efficient determinant approach to symbolic function generation for analog circuits

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems, 1992, p.827-830 vol.2

1992

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Low-power multirate architecture for IF digital frequency down converter

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 1998-11, Vol.45 (11), p.1487-1494

1998

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Low-Power Embedded DSP Core for Communication Systems

EURASIP Journal on Applied Signal Processing, 2003-12, Vol.2003 (13), p.232360-1370, Article 232360

2003

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A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

IEEE journal of solid-state circuits, 1997-01, Vol.32 (1), p.114-118

1997

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Decentralized BIST Methodology for System Level Interconnects

Journal of electronic testing, 1999-12, Vol.15 (3), p.255

1999

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Fixed-width multiplier for DSP application

Proceedings 2000 International Conference on Computer Design, 2000, p.318-322

2000

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Intrinsic response for analog module testing using an analog testability bus

ACM transactions on design automation of electronic systems, 2001-04, Vol.6 (2), p.226-243

2001

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A 12.5 Gbps CMOS input sampler for serial link receiver front end

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1055-1058 Vol. 2

2005

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Low-power self-timed circuit design technique

Electronics letters, 1997-01, Vol.33 (2), p.110

1997

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On-chip voltage down converter for low-power digital system: ISCAS'97

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 1998, Vol.45 (5), p.617-625

1998

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Jitter analysis of CBR streams in multimedia networks

Proceedings of 2003 IEEE Conference on Control Applications, 2003. CCA 2003, 2003, Vol.2, p.1339-1344 vol.2

2003

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QAM/VSB dual mode equalizer design and implementation

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360), 1999, p.323-326

1999

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Near-threshold all-digital PLL with dynamic voltage scaling power management

High throughput concurrent lookahead adaptive decision feedback equaliser

Low-error reduced-width Booth multipliers for DSP applications

Design techniques for high-speed multirate multistage FIR digital filters

Design and analysis of digital data recovery circuits using oversampling

Low switching noise and load-adaptive output buffer design techniques

Effect of chlorination bulking control on water quality and phosphate release/uptake in an anaerobic-oxic activated sludge system

A bibliometric study of semiconductor literature, 1978-1997

Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y Line

Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07)

Antiplatelet Constituents of Formosan Rubia akane

DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling

Flavonol Glycosides and Cytotoxic Triterpenoids from Alphitonia Philippinensis

An efficient determinant approach to symbolic function generation for analog circuits

Low-power multirate architecture for IF digital frequency down converter

Low-Power Embedded DSP Core for Communication Systems

A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

Decentralized BIST Methodology for System Level Interconnects

Fixed-width multiplier for DSP application

Intrinsic response for analog module testing using an analog testability bus

A 12.5 Gbps CMOS input sampler for serial link receiver front end

Low-power self-timed circuit design technique

On-chip voltage down converter for low-power digital system: ISCAS'97

Jitter analysis of CBR streams in multimedia networks

QAM/VSB dual mode equalizer design and implementation

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