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Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Microelectronics and reliability, 2016-06, Vol.61, p.64-70

2016

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Stress Analysis and Design Optimization for Low- k Chip With Cu Pillar Interconnection

IEEE transactions on components, packaging, and manufacturing technology (2011), 2015-09, Vol.5 (9), p.1273-1283

2015

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Failure Morphology After Drop Impact Test of Ball Grid Array (BGA) Package With Lead-Free Sn-3.8Ag-0.7Cu and Eutectic SnPb Solders

IEEE transactions on electronics packaging manufacturing, 2007-01, Vol.30 (1), p.49-53

2007

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Spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization during solid-state annealing

Journal of applied physics, 2004-06, Vol.95 (12), p.8286-8289

2004

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Squeegee bump technology

IEEE transactions on components and packaging technologies, 2002-03, Vol.25 (1), p.38-44

2002

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Characterization of lead-free solders and under bump metallurgies for flip-chip package

IEEE transactions on electronics packaging manufacturing, 2002-10, Vol.25 (4), p.300-307

2002

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Assembly Process and Warpage Management of Large Size through Silicon Interposer (38.7mm × 26.7mm) Package

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.1892-1898

2016

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Interfacial reaction of eutectic AuSi solder with Si (100) and Si (111) surfaces

Journal of applied physics, 2004-06, Vol.95 (11), p.6077-6081

2004

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Thermal Compression Bonding of 30um Pitch Cu Pillar Microbump on Organic Substrate with Bare Cu Bondpad

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.936-942

2016

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Electromigration studies of lead-free solder balls used for wafer-level packaging

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.717-721

2011

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Heterogeneous 2.5D integration on through silicon interposer

Applied physics reviews, 2015-06, Vol.2 (2), p.21308

2015

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Tensile fracture behaviors of solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps

Journal of materials research, 2004-06, Vol.19 (6), p.1826-1834

2004

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Design analysis of an electroless plating bath using CFD technique

IEEE transactions on electronics packaging manufacturing, 2000-10, Vol.23 (4), p.237-237

2000

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Design analysis of an electroless plating bath using CFD technique

IEEE transactions on electronics packaging manufacturing, 2000-10, Vol.23 (4), p.306-313

2000

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Development of compliant Cu pillar for flip chip package

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-4

2015

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Electromigration reliability and morphologies of Cu pillar with microbump under high current density stressing

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-4

2015

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Comprehensive study on reliability of chip-package interaction using Cu pillar joint onto low k chip

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014, p.288-293

2014

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Thermal compression bonding with non-conductive adhesive of 30μm pitch Cu pillar micro bumps on organic substrate with bare Cu bondpads

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014, p.438-443

2014

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Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip

2014 IEEE 16th Electronics Packaging Technology Conference (EPTC), 2014, p.574-578

2014

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Stress Analysis and Design Optimization for Low-[Formula Omitted] Chip With Cu Pillar Interconnection

IEEE transactions on components, packaging, and manufacturing technology (2011), 2015-09, Vol.5 (9), p.1273

2015

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Reliability evaluations of chip interconnect in lead-free solder systems

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345), 2002, p.1275-1280

2002

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Mitigation of warpage for large 2.5D Through Silicon Interposer (TSI) package assembly

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-6

2015

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Heterogeneous system implementation using through-silicon interposer (TSI) technology

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015, p.391-394

2015

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Development of fluxless flip chip reflow process for high density flip chip interconnect

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, p.1-6

2015

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Lead-free flip chip interconnect reliability for DCA and FC-PBGA packages

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546), 2004, Vol.1, p.642-649 Vol.1

2004

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Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Stress Analysis and Design Optimization for Low- k Chip With Cu Pillar Interconnection

Failure Morphology After Drop Impact Test of Ball Grid Array (BGA) Package With Lead-Free Sn-3.8Ag-0.7Cu and Eutectic SnPb Solders

Spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization during solid-state annealing

Squeegee bump technology

Characterization of lead-free solders and under bump metallurgies for flip-chip package

Assembly Process and Warpage Management of Large Size through Silicon Interposer (38.7mm × 26.7mm) Package

Interfacial reaction of eutectic AuSi solder with Si (100) and Si (111) surfaces

Thermal Compression Bonding of 30um Pitch Cu Pillar Microbump on Organic Substrate with Bare Cu Bondpad

Electromigration studies of lead-free solder balls used for wafer-level packaging

Heterogeneous 2.5D integration on through silicon interposer

Tensile fracture behaviors of solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps

Design analysis of an electroless plating bath using CFD technique

Design analysis of an electroless plating bath using CFD technique

Development of compliant Cu pillar for flip chip package

Electromigration reliability and morphologies of Cu pillar with microbump under high current density stressing

Comprehensive study on reliability of chip-package interaction using Cu pillar joint onto low k chip

Thermal compression bonding with non-conductive adhesive of 30μm pitch Cu pillar micro bumps on organic substrate with bare Cu bondpads

Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip

Stress Analysis and Design Optimization for Low-[Formula Omitted] Chip With Cu Pillar Interconnection

Reliability evaluations of chip interconnect in lead-free solder systems

Mitigation of warpage for large 2.5D Through Silicon Interposer (TSI) package assembly

Heterogeneous system implementation using through-silicon interposer (TSI) technology

Development of fluxless flip chip reflow process for high density flip chip interconnect

Lead-free flip chip interconnect reliability for DCA and FC-PBGA packages

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