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Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

IEEE transactions on electron devices, 2016-04, Vol.63 (4), p.1533-1538

2016

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Investigation of Hysteresis Phenomenon in Floating-Gate NAND Flash Memory Cells

IEEE transactions on electron devices, 2015-09, Vol.62 (9), p.2738-2744

2015

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Effect of Temperature and Electric Field on Degradation in Amorphous InGaZnO TFTs Under Positive Gate and Drain Bias Stress

IEEE electron device letters, 2014-04, Vol.35 (4), p.458-460

2014

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Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String

IEEE transactions on electron devices, 2011-01, Vol.58 (1), p.67-73

2011

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Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure

2015 Symposium on VLSI Technology (VLSI Technology), 2015, p.T182-T183

2015

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Extraction of Interface Trap Density in the Region Between Adjacent Wordlines in NAND Flash Memory Strings

IEEE electron device letters, 2015-01, Vol.36 (1), p.53-55

2015

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The Effect of Adjacent Bit-Line Cell Interference on Random Telegraph Noise in nand Flash Memory Cell Strings

IEEE transactions on electron devices, 2012-12, Vol.59 (12), p.3568-3573

2012

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Position-Dependent Threshold-Voltage Variation by Random Telegraph Noise in nand Flash Memory Strings

IEEE electron device letters, 2010-07, Vol.31 (7), p.635-637

2010

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Design Consideration of Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope

IEEE journal of the Electron Devices Society, 2016-09, Vol.4 (5), p.328-334

2016

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High-Density Three-Dimensional Stacked nand Flash With Common Gate Structure and Shield Layer

IEEE transactions on electron devices, 2011-12, Vol.58 (12), p.4212-4218

2011

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New Read Schemes Using Boosted Channel Potential of Adjacent Bit-Line Strings in nand Flash Memory

IEEE electron device letters, 2012-08, Vol.33 (8), p.1198-1200

2012

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A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.340-342

2018

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Machine-Learning-Based Read Reference Voltage Estimation for NAND Flash Memory Systems Without Knowledge of Retention Time

IEEE access, 2020, Vol.8, p.176416-176429

2020

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Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash memory

Semiconductor science and technology, 2014-12, Vol.29 (12)

2014

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Trap Profiling in Nitride Storage Layer in 3-D NAND Flash Memory Using Retention Characteristics and AC- \text} Method

IEEE electron device letters, 2015-06, Vol.36 (6), p.561-563

2015

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A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12(3), 47, pp.360-369

2012

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Characterization of random telegraph noise generated in the space region in NAND flash memory strings

Semiconductor science and technology, 2014-12, Vol.29 (12), p.125001

2014

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Analysis of Random Telegraph Noise and low frequency noise properties in 3-d stacked NAND flash memory with tube-type poly-Si channel structure

2012 Symposium on VLSI Technology (VLSIT), 2012, p.55-56

2012

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Effect of traps on transient bit-line current behavior in word-line stacked nand flash memory with poly-Si body

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

Japanese Journal of Applied Physics, 2011-10, Vol.50 (10), p.100204-100204-2

2011

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Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory

Japanese Journal of Applied Physics, 2013-04, Vol.52 (4), p.04CA07-04CA07-4

2013

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Cell Operation Technologies to Overcome Scale-down Issues in 3D NAND Flash Memory

2022 International Conference on Electronics, Information, and Communication (ICEIC), 2022, p.298-299

2022

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A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

Japanese Journal of Applied Physics, 2011-10, Vol.50 (10R), p.100204

2011

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A new read method suppressing effect of random telegraph noise in NAND flash memory by using hysteretic characteristic

2013 Symposium on VLSI Technology, 2013, p.T154-T155

2013

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Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure

2012 International Electron Devices Meeting, 2012, p.9.3.1-9.3.4

2012

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Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

Investigation of Hysteresis Phenomenon in Floating-Gate NAND Flash Memory Cells

Effect of Temperature and Electric Field on Degradation in Amorphous InGaZnO TFTs Under Positive Gate and Drain Bias Stress

Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String

Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure

Extraction of Interface Trap Density in the Region Between Adjacent Wordlines in NAND Flash Memory Strings

The Effect of Adjacent Bit-Line Cell Interference on Random Telegraph Noise in nand Flash Memory Cell Strings

Position-Dependent Threshold-Voltage Variation by Random Telegraph Noise in nand Flash Memory Strings

Design Consideration of Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope

High-Density Three-Dimensional Stacked nand Flash With Common Gate Structure and Shield Layer

New Read Schemes Using Boosted Channel Potential of Adjacent Bit-Line Strings in nand Flash Memory

A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

Machine-Learning-Based Read Reference Voltage Estimation for NAND Flash Memory Systems Without Knowledge of Retention Time

Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash memory

Trap Profiling in Nitride Storage Layer in 3-D NAND Flash Memory Using Retention Characteristics and AC- \text} Method

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

Characterization of random telegraph noise generated in the space region in NAND flash memory strings

Analysis of Random Telegraph Noise and low frequency noise properties in 3-d stacked NAND flash memory with tube-type poly-Si channel structure

Effect of traps on transient bit-line current behavior in word-line stacked nand flash memory with poly-Si body

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory

Cell Operation Technologies to Overcome Scale-down Issues in 3D NAND Flash Memory

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

A new read method suppressing effect of random telegraph noise in NAND flash memory by using hysteretic characteristic

Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure

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