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A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

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Extracting Mobility Degradation and Total Series Resistance of Cylindrical Gate-All-Around Silicon Nanowire Field-Effect Transistors

IEEE electron device letters, 2009-06, Vol.30 (6), p.665-667

2009

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Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017, p.61-72

2017

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Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2016, p.169-172

2016

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Considerations on highly scalable and easily stackable phase change memory cell array for low-cost and high-performance applications

2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), 2014, p.1-5

2014

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Co-existence of Random Telegraph Noise and Single-Hole-Tunneling State in Gate-All-Around PMOS Silicon Nanowire Field-Effect-Transistors

Journal of semiconductor technology and science, 2011, Vol.11 (2), p.80-87

2011

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Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2002, p.287-291

2002

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A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

2009 Symposium on VLSI Circuits, 2009, p.132-133

2009

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.390-391

2017

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23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.394-395

2017

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A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

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Mixed particle Monte Carlo method for deep submicron semiconductor device simulator

IEEE transactions on computer-aided design of integrated circuits and systems, 1991-12, Vol.10 (12), p.1534-1541

1991

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18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.316-317

2016

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.314-315

2016

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Novel Deep Trench Buried-Body-Contact (DBBC) of 4F2 cell for sub 30nm DRAM technology

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012, p.193-196

2012

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Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011, p.211-214

2011

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Co-existence of Random Telegraph Noise and Single-Hole-Tunneling State in Gate-All-Around PMOS Silicon Nanowire Field-Effect-Transistors

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2011, 11(2), 42, pp.80-87

2011

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A 31 ns Random Cycle VCAT-Based 4F2 DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010, Vol.45 (4), p.880-888

2010

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Process technology high-k ii: gate dielectrics

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest, 2005, p.412-412

2005

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Coniferyl aldehyde attenuates radiation enteropathy by inhibiting cell death and promoting endothelial cell function

PloS one, 2015-06, Vol.10 (6), p.e0128552-e0128552

2015

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A Simple Hot Electron Transport Model And Its Prediction Of Si-SiO/sub 2/ Injection Probability

[Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD), 1993, p.166-167

1993

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The characteristics of elderly suicidal attempters in the emergency department in Korea: a retrospective study

Journal of yeungnam medical science, 2024-01, Vol.41 (1), p.30-38

2024

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Propane dehydrogenation over Pt–Sn/Rare-earth-doped Al₂O₃: Influence of La, Ce, or Y on the formation and stability of Pt–Sn alloys

Catalysis today, 2011-04, Vol.164 (1), p.214-220

2011

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Hot electron transistors on silicon substrate (HESS)-a computational prototyping

Proceedings IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1995, p.229-233

1995

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The Effect of Tin–Support Interaction on Catalytic Stability over Pt–Sn/xAl–SBA-15 Catalysts for Propane Dehydrogenation

Catalysis letters, 2012-07, Vol.142 (7), p.838-844

2012

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A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

Extracting Mobility Degradation and Total Series Resistance of Cylindrical Gate-All-Around Silicon Nanowire Field-Effect Transistors

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)

Considerations on highly scalable and easily stackable phase change memory cell array for low-cost and high-performance applications

Co-existence of Random Telegraph Noise and Single-Hole-Tunneling State in Gate-All-Around PMOS Silicon Nanowire Field-Effect-Transistors

Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress

A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency

Mixed particle Monte Carlo method for deep submicron semiconductor device simulator

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

Novel Deep Trench Buried-Body-Contact (DBBC) of 4F2 cell for sub 30nm DRAM technology

Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)

Co-existence of Random Telegraph Noise and Single-Hole-Tunneling State in Gate-All-Around PMOS Silicon Nanowire Field-Effect-Transistors

A 31 ns Random Cycle VCAT-Based 4F2 DRAM With Manufacturability and Enhanced Cell Efficiency

Process technology high-k ii: gate dielectrics

Coniferyl aldehyde attenuates radiation enteropathy by inhibiting cell death and promoting endothelial cell function

A Simple Hot Electron Transport Model And Its Prediction Of Si-SiO/sub 2/ Injection Probability

The characteristics of elderly suicidal attempters in the emergency department in Korea: a retrospective study

Propane dehydrogenation over Pt–Sn/Rare-earth-doped Al₂O₃: Influence of La, Ce, or Y on the formation and stability of Pt–Sn alloys

Hot electron transistors on silicon substrate (HESS)-a computational prototyping

The Effect of Tin–Support Interaction on Catalytic Stability over Pt–Sn/xAl–SBA-15 Catalysts for Propane Dehydrogenation

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