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CNN-Based Stochastic Regression for IDDQ Outlier Identification

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

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Methodology of Generating Timing-Slack-Based Cell-Aware Tests

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.5057-5070

2022

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Physical-aware systematic multiple defect diagnosis

IET computers & digital techniques, 2014-09, Vol.8 (5), p.199-209

2014

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Methodology of generating dual-cell-aware tests

2017 IEEE 35th VLSI Test Symposium (VTS), 2017, p.1-6

2017

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Predicting Vt mean and variance from parallel Id measurement with model-fitting technique

2016 IEEE 34th VLSI Test Symposium (VTS), 2016, p.1-6

2016

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Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks

2021 IEEE 39th VLSI Test Symposium (VTS), 2021, p.1-7

2021

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CNN-based Stochastic Regression for IDDQ Outlier Identification

2020 IEEE 38th VLSI Test Symposium (VTS), 2020, p.1-6

2020

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Layout-Based Dual-Cell-Aware Tests

2019 IEEE 37th VLSI Test Symposium (VTS), 2019, p.1-6

2019

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Methodology of Generating Timing-Slack-Based Cell-Aware Tests

2019 IEEE International Test Conference (ITC), 2019, p.1-10

2019

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Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, p.426-431

2017

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Case study of yield learning through in-house flow of volume diagnosis

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT), 2013, p.1-4

2013

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A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design

2009 International Test Conference, 2009, p.1-10

2009

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Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks

IEEE transactions on semiconductor manufacturing, 2024-08, Vol.37 (3), p.280-292

2024

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Case study of process and design performance debugging with Digital Speed Sensor

VLSI Design, Automation and Test(VLSI-DAT), 2015, p.1-4

2015

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A Model-Based-Random-Forest Framework for Predicting V Mean and Variance Based on Parallel I Measurement

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-10, Vol.37 (10), p.2139-2151

2018

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A Model-Based-Random-Forest Framework for Predicting [Formula Omitted] Mean and Variance Based on Parallel [Formula Omitted] Measurement

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-01, Vol.37 (10), p.2139

2018

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Fault pattern oriented defect diagnosis for memories

International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.29-38

2003

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Experiences In Deep Sub-Micron Scan-Based At-Speed Delay Testing

2006 International Symposium on VLSI Design, Automation and Test, 2006, p.1-4

2006

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FAME: A Fault-Pattern Based Memory Failure Analysis Framework

International Conference on Computer Aided Design: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design; 09-13 Nov. 2003, 2003, p.595-595

2003

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