UB Paderborn / Katalog / Suche / in CDI

1 – 24 von 24

Sortiert nach

Compact Test Pattern Selection for Small Delay Defect

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-06, Vol.32 (6), p.971-975

2013

Volltextzugriff (PDF)

Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

Active and Passive Electronic Components, 2012-01, Vol.2012, p.1-10

2012

Volltextzugriff (PDF)

Multi-chains encoding scheme in low-cost ATE

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.1587-1590

2010

Volltextzugriff (PDF)

Reducing switching activity by test slice difference technique for test volume compression

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.2986-2989

2009

Volltextzugriff (PDF)

Multi-cycle compress technique for high-speed IP in low-cost environment

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.437-440

2010

Volltextzugriff (PDF)

The AB-filling methodology for power-aware at-speed scan testing

2010 IEEE International Test Conference, 2010, p.1-1

2010

Volltextzugriff (PDF)

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology

2009 Asian Test Symposium, 2009, p.105-110

2009

Volltextzugriff (PDF)

Test slice difference technique for low power encoding

2008 IEEE International High Level Design Validation and Test Workshop, 2008, p.25-32

2008

Volltextzugriff (PDF)

Power-aware compression scheme for multiple scan-chain

Journal of the Chinese Institute of Engineers, 2011-06, Vol.34 (4), p.515-527

2011

Volltextzugriff (PDF)

Low power multi-chains encoding scheme for SoC in low-cost environment

2009 International Test Conference, 2009, p.1-1

2009

Volltextzugriff (PDF)

Low-capture-power X-filling method based on architecture using selection expansion

2018 IEEE International Conference on Applied System Invention (ICASI), 2018, p.102-104

2018

Volltextzugriff (PDF)

Optimal unknown bit filtering for test response masking

2012 International Symposium on Intelligent Signal Processing and Communications Systems, 2012, p.787-791

2012

Volltextzugriff (PDF)

An efficient test-data compaction for low power VLSI testing

2008 IEEE International Conference on Electro/Information Technology, 2008, p.237-241

2008

Volltextzugriff (PDF)

A timing-driven pseudoexhaustive testing for VLSI circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-01, Vol.20 (1), p.147-158

2001

Volltextzugriff (PDF)

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006, p.1883-1886

2006

Volltextzugriff (PDF)

Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006, p.1399-1402

2006

Volltextzugriff (PDF)

Reconfigurable multiple scan-chains for reducing test application time of SOCs

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5846-5849 Vol. 6

2005

Volltextzugriff (PDF)

A novel reseeding mechanism for pseudo-random testing of VLSI circuits

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.2979-2982 Vol. 3

2005

Volltextzugriff (PDF)

A novel gated scan-cell scheme for low Capture Power (LCP) in at-speed testing

Proceedings of the 2009 12th International Symposium on Integrated Circuits, 2009, p.647-650

2009

Volltextzugriff (PDF)

A Scan-Based Lower-Power Testing Architecture for Modern Circuits

2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2021, p.1-2

2021

Volltextzugriff (PDF)

The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design

2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008, p.462-465

2008

Volltextzugriff (PDF)

An enhanced tree-structured scan chain for pseudo-exhaustive testing of VLSI circuits

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings, 2003, p.374-377

2003

Volltextzugriff (PDF)

A broadcast-based test scheme for reducing test size and application time

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

Volltextzugriff (PDF)

An efficient mechanism for debugging RTL description

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings, 2003, p.370-373

2003

Volltextzugriff (PDF)

1 – 24 von 24

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(4)
Mit Volltextzugriff
(22)

Publikationsform

Tagungsberichte
(20)
Artikel
(4)

Sprache

Englisch
(24)

Erscheinungsjahr

n.n

Thema

Science & Technology
(18)
Technology
(18)
Engineering
(16)
Engineering, Electrical & Electronic
(15)
Circuit Testing
(13)
Very Large Scale Integration
(11)
Computer Science
(10)
Computer Science, Hardware & Architecture
(9)
Circuit Faults
(8)
Power Dissipation
(8)
Hardware
(7)
Design For Testability
(6)
Automatic Test Pattern Generation
(5)
Fault Detection
(5)
Flip-Flops
(5)
Pins
(5)
Test Data Compression
(5)
Built-In Self-Test
(4)
Electrical Fault Detection
(4)
Encoding
(4)

15 weitere anzeigen...

Weniger anzeigen...

Kollektion

IEL
(22)
Ingenta
(4)
EZB Electronic Journals Library
(2)
Taylor & Francis Journals Complete
(1)
Business Source Ultimate
(1)
IngentaConnect Journals
(1)
Taylor & Francis Journals Auto-Holdings Collection
(1)
Taylor & Francis
(1)

3 weitere anzeigen...

Weniger anzeigen...

Zeitschrift / Serie

Menü

Weitere Dienste

Einstellungen

Compact Test Pattern Selection for Small Delay Defect

Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

Multi-chains encoding scheme in low-cost ATE

Reducing switching activity by test slice difference technique for test volume compression

Multi-cycle compress technique for high-speed IP in low-cost environment

The AB-filling methodology for power-aware at-speed scan testing

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology

Test slice difference technique for low power encoding

Power-aware compression scheme for multiple scan-chain

Low power multi-chains encoding scheme for SoC in low-cost environment

Low-capture-power X-filling method based on architecture using selection expansion

Optimal unknown bit filtering for test response masking

An efficient test-data compaction for low power VLSI testing

A timing-driven pseudoexhaustive testing for VLSI circuits

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits

Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs

Reconfigurable multiple scan-chains for reducing test application time of SOCs

A novel reseeding mechanism for pseudo-random testing of VLSI circuits

A novel gated scan-cell scheme for low Capture Power (LCP) in at-speed testing

A Scan-Based Lower-Power Testing Architecture for Modern Circuits

The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design

An enhanced tree-structured scan chain for pseudo-exhaustive testing of VLSI circuits

A broadcast-based test scheme for reducing test size and application time

An efficient mechanism for debugging RTL description

Suchergebnisse filtern