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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

IEEE journal of solid-state circuits, 2016-04, Vol.51 (4), p.930-942

2016

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Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors

IEEE transactions on very large scale integration (VLSI) systems, 2015-04, Vol.23 (4), p.723-730

2015

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Multiple-Input Relay Design for More Compact Implementation of Digital Logic Circuits

IEEE electron device letters, 2012-02, Vol.33 (2), p.281-283

2012

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Technology Variability From a Design Perspective

IEEE transactions on circuits and systems. I, Regular papers, 2011-09, Vol.58 (9), p.1996-2009

2011

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EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation

IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1061-1072

2021

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Power Estimation of Embedded Multiplier Blocks in FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2010-05, Vol.18 (5), p.835-839

2010

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Methodology for Complete Decorrelation of Power Supply EM Side-Channel Signal and Sensitive Data

IEEE transactions on circuits and systems. II, Express briefs, 2022-04, Vol.69 (4), p.2256-2260

2022

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Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits

IEEE transactions on industrial informatics, 2014-02, Vol.10 (1), p.393-398

2014

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A complete dynamic power estimation model for data-paths in FPGA DSP designs

Integration (Amsterdam), 2012-03, Vol.45 (2), p.172-185

2012

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An Agile Approach to Building RISC-V Microprocessors

IEEE MICRO, 2016-03, Vol.36 (2), p.8-20

2016

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A Low-Latency, Low-Power FPGA Implementation of ECG Signal Characterization Using Hermite Polynomials

Electronics (Basel), 2021-10, Vol.10 (19), p.2324

2021

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Power Measurement Methodology for FPGA Devices

IEEE transactions on instrumentation and measurement, 2011-01, Vol.60 (1), p.237-247

2011

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Analytical High-Level Power Model for LUT-Based Components

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p.369-378

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Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes

Journal of systems architecture, 2014-08, Vol.60 (7), p.579-591

2014

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Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models

International journal of electronics, 2008-07, Vol.95 (7), p.653-668

2008

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A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2233-2236

2015

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Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018, p.243-247

2018

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Hardware emulation of ECG sensors for biomedical embedded system design and teaching

2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon), 2022, p.1-6

2022

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Side-channel Attack Countermeasure Based on Power Supply Modulation

2022 30th European Signal Processing Conference (EUSIPCO), 2022, p.618-622

2022

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Switching Activity Models for Power Estimation in FPGA Multipliers

Reconfigurable Computing: Architectures, Tools and Applications, p.201-213

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PATMOS 2019 Welcome Message

2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, p.i-i

2019

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Welcome Message

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018, p.1-1

2018

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Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C320-C321

2015

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A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C316-C317

2015

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Power estimation of dividers implemented in FPGAs

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011, p.313-318

2011

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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors

Multiple-Input Relay Design for More Compact Implementation of Digital Logic Circuits

Technology Variability From a Design Perspective

EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation

Power Estimation of Embedded Multiplier Blocks in FPGAs

Methodology for Complete Decorrelation of Power Supply EM Side-Channel Signal and Sensitive Data

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits

A complete dynamic power estimation model for data-paths in FPGA DSP designs

An Agile Approach to Building RISC-V Microprocessors

A Low-Latency, Low-Power FPGA Implementation of ECG Signal Characterization Using Hermite Polynomials

Power Measurement Methodology for FPGA Devices

Analytical High-Level Power Model for LUT-Based Components

Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes

Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator

Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices

Hardware emulation of ECG sensors for biomedical embedded system design and teaching

Side-channel Attack Countermeasure Based on Power Supply Modulation

Switching Activity Models for Power Estimation in FPGA Multipliers

PATMOS 2019 Welcome Message

Welcome Message

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

Power estimation of dividers implemented in FPGAs

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