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Implementation and evaluation of a microthread architecture

Journal of systems architecture, 2009-03, Vol.55 (3), p.149-161

2009

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Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings

1, 2006

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Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines

Proceedings 6th Australasian Computer Systems Architecture Conference. ACSAC 2001, 2001, p.80-88

Jesshope, C.

2001

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An implementation of the SANE Virtual Processor using POSIX threads

Journal of systems architecture, 2009-03, Vol.55 (3), p.162-169

2009

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μTC – An Intermediate Language for Programming Chip Multiprocessors

Advances in Computer Systems Architecture, 2006, p.147-160

2006

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Using branch prediction information for near-optimal I-cache leakage

Lecture notes in computer science, 2006, p.24-37

2006

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Scientific computing applications on the imagine stream processor

Lecture notes in computer science, 2006, p.38-51

2006

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Multi-threaded Microprocessors – Evolution or Revolution

Advances in Computer Systems Architecture, 2003, p.21-45

2003

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Register allocation on stream processor with local register file

Lecture notes in computer science, 2006, p.545-551

2006

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The algorithm and circuit design of a 400MHz 16-bit hybrid multiplier

Lecture notes in computer science, 2006, p.401-408

2006

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Research on petersen graphs and hyper-cubes connected interconnection networks

Lecture notes in computer science, 2006, p.495-501

2006

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Enhancing ICOUNT2.8 fetch policy with better fairness for SMT processors

Lecture notes in computer science, 2006, p.459-465

2006

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A 0-1 integer linear programming based approach for global locality optimizations

Lecture notes in computer science, 2006, p.281-294

2006

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A heterogeneous multi-core processor architecture for high performance computing

Lecture notes in computer science, 2006, p.359-365

2006

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A novel processor architecture for real-time control

Lecture notes in computer science, 2006, p.270-280

2006

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Optimization and evaluating of StreamYGX2 on MASA stream processor

Lecture notes in computer science, 2006, p.531-537

2006

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PMPS(3) : A performance model of parallel systems

Lecture notes in computer science, 2006, p.344-350

2006

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Static WCET analysis based compiler-directed DVS energy optimization in real-time applications

Lecture notes in computer science, 2006, p.123-136

2006

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Acceleration techniques for chip-multiprocessor simulator debug

Lecture notes in computer science, 2006, p.509-515

2006

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Compile-time thread distinguishment algorithm on VIM-based architecture

Lecture notes in computer science, 2006, p.559-566

2006

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Live range aware cache architecture

Lecture notes in computer science, 2006, p.409-415

2006

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Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination

Advances in Computer Systems Architecture, 2006, p.52-66

2006

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A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster

Advances in Computer Systems Architecture, 2006, p.231-243

2006

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Reorganizing UNIX for Reliability

Advances in Computer Systems Architecture, 2006, p.81-94

2006

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Processor Directed Dynamic Page Policy

Advances in Computer Systems Architecture, 2006, p.109-122

2006

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Implementation and evaluation of a microthread architecture

Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings

Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines

An implementation of the SANE Virtual Processor using POSIX threads

μTC – An Intermediate Language for Programming Chip Multiprocessors

Using branch prediction information for near-optimal I-cache leakage

Scientific computing applications on the imagine stream processor

Multi-threaded Microprocessors – Evolution or Revolution

Register allocation on stream processor with local register file

The algorithm and circuit design of a 400MHz 16-bit hybrid multiplier

Research on petersen graphs and hyper-cubes connected interconnection networks

Enhancing ICOUNT2.8 fetch policy with better fairness for SMT processors

A 0-1 integer linear programming based approach for global locality optimizations

A heterogeneous multi-core processor architecture for high performance computing

A novel processor architecture for real-time control

Optimization and evaluating of StreamYGX2 on MASA stream processor

PMPS(3) : A performance model of parallel systems

Static WCET analysis based compiler-directed DVS energy optimization in real-time applications

Acceleration techniques for chip-multiprocessor simulator debug

Compile-time thread distinguishment algorithm on VIM-based architecture

Live range aware cache architecture

Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination

A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster

Reorganizing UNIX for Reliability

Processor Directed Dynamic Page Policy

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