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MOBO-Driven Advanced Sub-3-nm Device Optimization for Enhanced PDP Performance

IEEE transactions on electron devices, 2024-05, Vol.71 (5), p.2881-2887

2024

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Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors

Electronics (Basel), 2022-09, Vol.11 (17), p.2761

2022

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Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors

IEEE journal of the Electron Devices Society, 2023, Vol.11, p.153-160

2023

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Enhancement and Expansion of the Neural Network-Based Compact Model Using a Binning Method

IEEE journal of the Electron Devices Society, 2024-01, Vol.12, p.1-1

2024

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Expanding the Pareto Front of Ferroelectric Field-Effect Transistors With a Dual-k Spacer

IEEE transactions on electron devices, 2024-10, Vol.71 (10), p.6009-6015

2024

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Efficient Design and Performance Analysis of a Hardware Right-shift Binary Modular Inversion Algorithm in GF(p)

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(3), 75, pp.425-437

2017

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CAD for nanometer silicon design challenges and success

IEEE transactions on very large scale integration (VLSI) systems, 2004-11, Vol.12 (11), p.1132-1147

Kong, Jeong-Taek

2004

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Programming Characteristics of Phase Change Random Access Memory Using Phase Change Simulations

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2701

2005

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A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

IEEE transactions on nanotechnology, 2002-12, Vol.1 (4), p.226-232

2002

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SoC in Nanoera: Challenges and Endless Possibility

Design, Automation and Test in Europe, 2005, p.2-2

Kong, Jeong-Taek

2005

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Analysis of hardware modular inversion modules for elliptic curve cryptography

2015 International SoC Design Conference (ISOCC), 2015, p.313-314

2015

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Simulation of Photoresist Thermal Flow Process with Viscous Flow Model

Japanese Journal of Applied Physics, 2004-09, Vol.43 (9R), p.6020, Article 6020

2004

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Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

Design, Automation and Test in Europe, 2005, p.138-139

2005

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Efficient Design and Performance Analysis of a Hardware Right-shift Binary Modular Inversion Algorithm in GF(p)

Journal of semiconductor technology and science, 2017, Vol.17 (3), p.425-437

2017

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Low-power dual-supply clock networks with clock gating and frequency doubling

IEICE Electronics Express, 2012, Vol.9 (6), p.502-508

2012

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An MTCMOS design methodology and its application to mobile computing

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03, 2003, p.110-115

2003

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Thermal Stress Model for Phase Change Random Access Memory

Solid state phenomena, 2007-06, Vol.124-126, p.37-40

2007

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3-Dimensional Analysis on the GIDL Current of Body-tied Triple Gate FinFET

2006 International Conference on Simulation of Semiconductor Processes and Devices, 2006, p.267-270

2006

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Analysis of Electronic Threshold of PRAM Cell Operation

2006 International Conference on Simulation of Semiconductor Processes and Devices, 2006, p.393-396

2006

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ViP: A Practical Approach to Platform-based System Modeling Methodology

Journal of semiconductor technology and science, 2005, Vol.5 (2), p.89-101

2005

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Methods to improve digital MOS macromodel accuracy

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-07, Vol.14 (7), p.868-881

1995

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A Unified Statistical Model for Inter-Die and Intra-Die Process Variation

2005 International Conference On Simulation of Semiconductor Processes and Devices, 2005, p.131-134

2005

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System Level Architecture Evaluation and Optimization : an Industrial Case Study with AMBA3 AXI

Journal of semiconductor technology and science, 2005, Vol.5 (4), p.229-236

2005

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An Industrial Case Study of the ARM926EJ-S Power Modeling

Journal of semiconductor technology and science, 2005, Vol.5 (4), p.221-228

2005

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Panel: design challenges for next-generation multimedia, game and entertainment platforms

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.459-459

2006

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MOBO-Driven Advanced Sub-3-nm Device Optimization for Enhanced PDP Performance

Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors

Enhancement and Expansion of the Neural Network-Based Compact Model Using a Binning Method

Expanding the Pareto Front of Ferroelectric Field-Effect Transistors With a Dual-k Spacer

Efficient Design and Performance Analysis of a Hardware Right-shift Binary Modular Inversion Algorithm in GF(p)

CAD for nanometer silicon design challenges and success

Programming Characteristics of Phase Change Random Access Memory Using Phase Change Simulations

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

SoC in Nanoera: Challenges and Endless Possibility

Analysis of hardware modular inversion modules for elliptic curve cryptography

Simulation of Photoresist Thermal Flow Process with Viscous Flow Model

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

Efficient Design and Performance Analysis of a Hardware Right-shift Binary Modular Inversion Algorithm in GF(p)

Low-power dual-supply clock networks with clock gating and frequency doubling

An MTCMOS design methodology and its application to mobile computing

Thermal Stress Model for Phase Change Random Access Memory

3-Dimensional Analysis on the GIDL Current of Body-tied Triple Gate FinFET

Analysis of Electronic Threshold of PRAM Cell Operation

ViP: A Practical Approach to Platform-based System Modeling Methodology

Methods to improve digital MOS macromodel accuracy

A Unified Statistical Model for Inter-Die and Intra-Die Process Variation

System Level Architecture Evaluation and Optimization : an Industrial Case Study with AMBA3 AXI

An Industrial Case Study of the ARM926EJ-S Power Modeling

Panel: design challenges for next-generation multimedia, game and entertainment platforms

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