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Characteristics of Using Oriental Medicine Clinics during the Japanese Occupation: An Analysis of the 1931 Seoul Bochun Clinic Account Book

Daehan yisa haghoeji, 2024-04, Vol.33 (1), p.59-101

2024

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A steep switching WSe2 impact ionization field-effect transistor

Nature communications, 2022-10, Vol.13 (1), p.6076-6076, Article 6076

2022

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Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

IEEE transactions on electron devices, 2016-12, Vol.63 (12), p.4674-4677

2016

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Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

Electronics (Basel), 2021-01, Vol.10 (2), p.180

2021

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Evaluation of various phase-transition materials for steep switching super-low power application in the latest technology node

Results in physics, 2024-05, Vol.60, p.107619, Article 107619

2024

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Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

AIP advances, 2023-04, Vol.13 (4), p.045211-045211-13

2023

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Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices

Micromachines (Basel), 2024-04, Vol.15 (4), p.450

2024

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Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5284-5287

2017

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Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

NPJ 2D materials and applications, 2024-04, Vol.8 (1), p.29-9, Article 29

2024

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Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

Nanomaterials (Basel, Switzerland), 2022-07, Vol.12 (13), p.2299

2022

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Self-heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs

IEEE access, 2023-01, Vol.11, p.1-1

2023

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Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)

IEEE access, 2023, Vol.11, p.97778-97785

2023

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Circuit simulation of floating-gate FET (FGFET) for logic application

Memories - Materials, Devices, Circuits and Systems, 2023-12, Vol.6, p.100090, Article 100090

2023

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Investigation on the effects of interconnect RC in 3nm technology node using Path-Finding Process Design Kit

IEEE access, 2022, Vol.10, p.1-1

2022

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Efficacy and safety of choline alphoscerate for amnestic mild cognitive impairment: a randomized double-blind placebo-controlled trial

BMC geriatrics, 2024-09, Vol.24 (1), p.774-10, Article 774

2024

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Shot noise effect on noise source and noise parameter of 10-nm-scale quasi-ballistic n-/p-type MOS devices

Japanese Journal of Applied Physics, 2016-05, Vol.55 (5), p.54102

2016

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Modulation of Contact Resistance of Dual‐Gated MoS2 FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts

Advanced science, 2023-07, Vol.10 (21), p.e2301400-n/a

2023

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Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2023, 23(4), 112, pp.215-227

2023

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Stromal vascular fraction from adipose tissue forms profound vascular network through the dynamic reassembly of blood endothelial cells

Arteriosclerosis, thrombosis, and vascular biology, 2011-05, Vol.31 (5), p.1141-1150

2011

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Temporal Noise Analysis and Reduction Method in CMOS Image Sensor Readout Circuit

IEEE transactions on electron devices, 2009-11, Vol.56 (11), p.2489-2495

2009

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Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

Nanomaterials (Basel, Switzerland), 2022-02, Vol.12 (4), p.591

2022

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Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation

IEEE journal of the Electron Devices Society, 2024, Vol.12, p.745-751

2024

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Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

Nanomaterials (Basel, Switzerland), 2022-11, Vol.12 (22), p.4096

2022

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Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

IEEE access, 2023, Vol.11, p.70691-70697

2023

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Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating

IEEE electron device letters, 2014-12, Vol.35 (12), p.1191-1193

2014

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Characteristics of Using Oriental Medicine Clinics during the Japanese Occupation: An Analysis of the 1931 Seoul Bochun Clinic Account Book

A steep switching WSe2 impact ionization field-effect transistor

Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

Evaluation of various phase-transition materials for steep switching super-low power application in the latest technology node

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices

Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET

Logic-in-memory application of ferroelectric-based WS2-channel field-effect transistors for improved area and energy efficiency

Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

Self-heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs

Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)

Circuit simulation of floating-gate FET (FGFET) for logic application

Investigation on the effects of interconnect RC in 3nm technology node using Path-Finding Process Design Kit

Efficacy and safety of choline alphoscerate for amnestic mild cognitive impairment: a randomized double-blind placebo-controlled trial

Shot noise effect on noise source and noise parameter of 10-nm-scale quasi-ballistic n-/p-type MOS devices

Modulation of Contact Resistance of Dual‐Gated MoS2 FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts

Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest Process Nodes

Stromal vascular fraction from adipose tissue forms profound vascular network through the dynamic reassembly of blood endothelial cells

Temporal Noise Analysis and Reduction Method in CMOS Image Sensor Readout Circuit

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation

Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node

Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits

Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating

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