UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Advancing Lung Cancer Treatment with Combined c-Met Promoter-Driven Oncolytic Adenovirus and Rapamycin

Cells (Basel, Switzerland), 2024-09, Vol.13 (18), p.1597

2024

Volltextzugriff (PDF)

Temperature-Aware Placement for SOCs

Proceedings of the IEEE, 2006-08, Vol.94 (8), p.1502-1518

2006

Volltextzugriff (PDF)

Electrochemically deposited nano polyaniline films as hole transporting layers in organic solar cells

Solar energy materials and solar cells, 2014-09, Vol.128, p.198-203

2014

Volltextzugriff (PDF)

Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-04, Vol.23 (4), p.565-572

2004

Volltextzugriff (PDF)

Heterologous protection in pigs induced by a plasmid-cured and crp gene-deleted Salmonella choleraesuis live vaccine

Vaccine, 2007-10, Vol.25 (41), p.7031-7040

2007

Volltextzugriff (PDF)

A yield improvement methodology using pre- and post-silicon statistical clock scheduling

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.611-618

2004

Volltextzugriff (PDF)

Thermal and power integrity based power/ground networks optimization

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.830-835 Vol.2

2004

Volltextzugriff (PDF)

False path and clock scheduling based yield-aware gate sizing

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005, p.423-426

2005

Volltextzugriff (PDF)

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005, 2005, p.575-581

2005

Volltextzugriff (PDF)

Yield-driven, false-path-aware clock skew scheduling

IEEE design & test of computers, 2005-05, Vol.22 (3), p.214-222

2005

Volltextzugriff (PDF)

HiSIM: hierarchical interconnect-centric circuit simulator

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.489-496

2004

Volltextzugriff (PDF)

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, p.1168-1171

2005

Volltextzugriff (PDF)

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 2005, Vol.2, p.1168-1171 Vol. 2

2005

Volltextzugriff (PDF)

Heterologous protection in pigs induced by a plasmid-cured andcrpgene-deletedSalmonella choleraesuislive vaccine

Vaccine, 2007-10, Vol.25 (41), p.7031

2007

Volltextzugriff (PDF)

Temperature-aware placement for SOCs: On-chip thermal engineering

Proceedings of the IEEE, 2006, Vol.94 (8), p.1502-1518

2006

Volltextzugriff (PDF)

Clock tree synthesis for timing convergence and timing yield improvement in nanometer technologies

Tsai, Jeng-Liang

2005

Volltextzugriff (PDF)

Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

Volltextzugriff (PDF)

Manufacturability and power in layout

International Conference on Computer Aided Design: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design : San Jose, California, 2006

2006

Volltextzugriff (PDF)

Asymmetric Synthesis of Spirooxindole δ‐Lactones with Vicinal Tertiary and Quaternary Stereocenters via Regio‐, Diastereo‐, and Enantioselective Organocatalytic Vinylogous Aldol‐cyclization Cascade Reaction

Advanced synthesis & catalysis, 2017-11, Vol.359 (22), p.4043-4049

2017

Volltextzugriff (PDF)

Sensitivity guided net weighting for placement driven synthesis

Proceedings of the 2004 international symposium on Physical design, 2004, p.124-131

2004

Volltextzugriff (PDF)

Thermal and Power Integrity Based Power/Ground Networks Optimization

Proceedings of the conference on Design, automation and test in Europe - Volume 2, 2004, p.20830-20830

2004

Volltextzugriff (PDF)

Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time

International Symposium on Physical Design: Proceedings of the 2003 international symposium on Physical design; 06-09 Apr. 2003, 2003, p.166-173

2003

Volltextzugriff (PDF)

Sensitivity guided net weighting for placement driven synthesis

International Symposium on Physical Design: Proceedings of the 2004 international symposium on Physical design; 18-21 Apr. 2004, 2004, p.10-17

2004

Volltextzugriff (PDF)

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

International Conference on Computer Aided Design: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design; 06-10 Nov. 2005, 2005, p.575-581

2005

Volltextzugriff (PDF)

Self-management of greenhouse gas and air pollutant emissions in Taichung Port, Taiwan

Transportation research. Part D, Transport and environment, 2018-08, Vol.63, p.576-587

2018

Volltextzugriff (PDF)

1 – 25 von 31

Menü

Weitere Dienste

Einstellungen

Advancing Lung Cancer Treatment with Combined c-Met Promoter-Driven Oncolytic Adenovirus and Rapamycin

Temperature-Aware Placement for SOCs

Electrochemically deposited nano polyaniline films as hole transporting layers in organic solar cells

Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing

Heterologous protection in pigs induced by a plasmid-cured and crp gene-deleted Salmonella choleraesuis live vaccine

A yield improvement methodology using pre- and post-silicon statistical clock scheduling

Thermal and power integrity based power/ground networks optimization

False path and clock scheduling based yield-aware gate sizing

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

Yield-driven, false-path-aware clock skew scheduling

HiSIM: hierarchical interconnect-centric circuit simulator

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Heterologous protection in pigs induced by a plasmid-cured andcrpgene-deletedSalmonella choleraesuislive vaccine

Temperature-aware placement for SOCs: On-chip thermal engineering

Clock tree synthesis for timing convergence and timing yield improvement in nanometer technologies

Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method

Manufacturability and power in layout

Asymmetric Synthesis of Spirooxindole δ‐Lactones with Vicinal Tertiary and Quaternary Stereocenters via Regio‐, Diastereo‐, and Enantioselective Organocatalytic Vinylogous Aldol‐cyclization Cascade Reaction

Sensitivity guided net weighting for placement driven synthesis

Thermal and Power Integrity Based Power/Ground Networks Optimization

Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time

Sensitivity guided net weighting for placement driven synthesis

Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

Self-management of greenhouse gas and air pollutant emissions in Taichung Port, Taiwan

Suchergebnisse filtern