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Colonoscopy in Zaria: Indications and findings

Nigerian journal of clinical practice, 2022-09, Vol.25 (9), p.1580-1583

2022

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Subsidence and Uplift History of the UAE and the Western Flank of the UAE‐Oman Mountain Range

Tectonics (Washington, D.C.), 2023-10, Vol.42 (10)

2023

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Demographic profile and endoscopic findings among patients with upper gastrointestinal bleeding in Ahmadu Bello University Teaching Hospital, Zaria, North-Western Nigeria

Nigerian journal of clinical practice, 2020-08, Vol.23 (8), p.1163-1166, Article 1163

2020

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Simplified bit parallel systolic multipliers for special class of Galois field (2m) with testability

IET computers & digital techniques, 2010-09, Vol.4 (5), p.428-437

2010

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On the synthesis of bit-parallel Galois field multipliers with on-line SEC and DED

International journal of electronics, 2009-11, Vol.96 (11), p.1161-1173

2009

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Efficient Parathyroidectomy Guided by SPECT-MIBI and Hormonal Measurements

The Journal of nuclear medicine (1978), 1996-05, Vol.37 (5), p.798-804

1996

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A Galois field-based logic synthesis with testability

IET computers & digital techniques, 2010-07, Vol.4 (4), p.263-273

2010

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Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

Computers & electrical engineering, 2013-05, Vol.39 (4), p.1077-1087

2013

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MO-0304 Dosimetric comparison of ACE algorithm and TG-43 formalism in HDR brachytherapy of carcinoma cervix

Radiotherapy and oncology, 2022-05, Vol.170, p.S266-S266

2022

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Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)

IEEE transactions on computers, 2008-09, Vol.57 (9), p.1289-1294

2008

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Single error correctable bit parallel multipliers over GF(2m)

IET computers & digital techniques, 2009-05, Vol.3 (3), p.281-288

2009

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C-testable bit parallel multipliers over GF (2 m )

ACM transactions on design automation of electronic systems, 2008-01, Vol.13 (1), p.1-18

2008

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Fault tolerant bit parallel finite field multipliers using LDPC codes

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1684-1687

2008

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Preoperative Scintigraphy and Operative Probe Scintimetry of Colorectal Carcinoma Using Technetium-99m-88BV59

The Journal of nuclear medicine (1978), 1995-05, Vol.36 (5), p.738-745

1995

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99mTc-HMPAO SPECT of the brain in mild to moderate traumatic brain injury patients: Compared with CT-a prospective study

Brain injury, 1993-11, Vol.7 (6), p.469-479

1993

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A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields

IEEE transactions on computers, 2007-08, Vol.56 (8), p.1119-1132

2007

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GfXpress: A Technique for Synthesis and Optimization of [Formula Omitted] Polynomials

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-04, Vol.27 (4), p.698

2008

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Fault detection and repair of DSC arrays through memristor sensing

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015, p.7-12

2015

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A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

IEEE transactions on computers, 2007-08, Vol.56 (8), p.1133-1145, Article 1133

2007

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On the design of different concurrent EDC schemes for S-Box and GF(p)

2010 11th International Symposium on Quality Electronic Design (ISQED), 2010, p.211-218

2010

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Multiple Bit Error Detection and Correction in GF Arithmetic Circuits

2010 International Symposium on Electronic System Design, 2010, p.101-106

2010

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On the synthesis of attack tolerant cryptographic hardware

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2010, p.286-291

2010

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Single Error Correcting Finite Field Multipliers Over GF(2m)

21st International Conference on VLSI Design (VLSID 2008), 2008, p.33-38

2008

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VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m)Using Dual Bases

Progress in VLSI Design and Test, p.258-269

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Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)

2006 IEEE International High Level Design Validation and Test Workshop, 2006, p.48-54

2006

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Colonoscopy in Zaria: Indications and findings

Subsidence and Uplift History of the UAE and the Western Flank of the UAE‐Oman Mountain Range

Demographic profile and endoscopic findings among patients with upper gastrointestinal bleeding in Ahmadu Bello University Teaching Hospital, Zaria, North-Western Nigeria

Simplified bit parallel systolic multipliers for special class of Galois field (2m) with testability

On the synthesis of bit-parallel Galois field multipliers with on-line SEC and DED

Efficient Parathyroidectomy Guided by SPECT-MIBI and Hormonal Measurements

A Galois field-based logic synthesis with testability

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity

MO-0304 Dosimetric comparison of ACE algorithm and TG-43 formalism in HDR brachytherapy of carcinoma cervix

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)

Single error correctable bit parallel multipliers over GF(2m)

C-testable bit parallel multipliers over GF (2 m )

Fault tolerant bit parallel finite field multipliers using LDPC codes

Preoperative Scintigraphy and Operative Probe Scintimetry of Colorectal Carcinoma Using Technetium-99m-88BV59

99mTc-HMPAO SPECT of the brain in mild to moderate traumatic brain injury patients: Compared with CT-a prospective study

A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields

GfXpress: A Technique for Synthesis and Optimization of [Formula Omitted] Polynomials

Fault detection and repair of DSC arrays through memristor sensing

A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

On the design of different concurrent EDC schemes for S-Box and GF(p)

Multiple Bit Error Detection and Correction in GF Arithmetic Circuits

On the synthesis of attack tolerant cryptographic hardware

Single Error Correcting Finite Field Multipliers Over GF(2m)

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m)Using Dual Bases

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)

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