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A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs

IEEE journal of solid-state circuits, 2007-11, Vol.42 (11), p.2611-2619

2007

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An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

IEEE transactions on electron devices, 2003-06, Vol.50 (6), p.1451-1458

2003

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A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.365-371

2008

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A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

IEEE journal of solid-state circuits, 2007-04, Vol.42 (4), p.853-861

2007

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Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's

IEEE transactions on electron devices, 1999-08, Vol.46 (8), p.1693-1698

1999

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Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

IEEE transactions on electron devices, 2001-09, Vol.48 (9), p.2065-2073

2001

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Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

IEEE transactions on electron devices, 2001-12, Vol.48 (12), p.2816-2822

2001

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An analytical method of evaluating variation of the threshold voltage shift caused by the negative-bias temperature stress in poly-Si TFTs

IEEE transactions on electron devices, 1998-01, Vol.45 (1), p.165-172

1998

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Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

IEEE transactions on electron devices, 1999-01, Vol.46 (1), p.151-158

1999

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Robotic crowd biology with Maholo LabDroids

Nature biotechnology, 2017-04, Vol.35 (4), p.310-312

2017

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Mechanism of negative-bias temperature instability in polycrystalline-silicon thin film transistors

Journal of applied physics, 1994-12, Vol.76 (12), p.8160-8166

1994

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A capacitorless twin-transistor random access memory (TTRAM) on SOI

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.435-438

2005

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Evaluation of surface defects on SIMOX and their influences on device characteristics

Journal of crystal growth, 2000-03, Vol.210 (1), p.40-44

2000

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Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate

2008 Symposium on VLSI Technology, 2008, p.166-167

2008

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Impact of a vertical Φ-shape transistor (VΦT) cell for 1 Gbit DRAM and beyond

IEEE transactions on electron devices, 1995-12, Vol.42 (12), p.2117-2123

1995

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Investigation of anomalous leakage current in mesa-isolated SOI MOSFETs

IEEE electron device letters, 1997-10, Vol.18 (10), p.499-502

1997

Volltextzugriff (PDF)

Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si

IEEE transactions on electron devices, 1995-06, Vol.42 (6), p.1106-1112

1995

Volltextzugriff (PDF)

Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits

IEEE transactions on electron devices, 1998-07, Vol.45 (7), p.1479-1486

1998

Volltextzugriff (PDF)

A 400MHz 183mW microcontroller in body-tied SOI technology

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC, 2003, p.110-481 vol.1

2003

Volltextzugriff (PDF)

Novel SOI wafer engineering using low stress and high mobility CMOSFET with -channel for embedded RF/analog applications

Digest. International Electron Devices Meeting, 2002, p.663-666

2002

Volltextzugriff (PDF)

LPE crystal growth and magnetophonon resonance recombination of Hg1-xMnxTe

Solid state communications, 1985-11, Vol.56 (7), p.603-606

1985

Volltextzugriff (PDF)

Cornerless active area cell and Bi-T-MOS process for sub-half micron SRAMs

Digest of technical papers - Symposium on VLSI Technology, 1994, p.103-104

1994

Volltextzugriff (PDF)

Vertical Phi -shape transistor (V Phi T) cell for 1Gbit DRAM and beyond

Digest of technical papers - Symposium on VLSI Technology, 1994, p.133-134

1994

Volltextzugriff (PDF)

Auger recombination oscillation of magnetoresistance in Hg1-xCdxTe under heated electron and hole condition

Solid state communications, 1985-11, Vol.56 (7), p.599-602

1985

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Magnetophonon resonance recombination of hot carriers with emission of two TA-phonons in LPE-HgTe

Solid state communications, 1984, Vol.52 (12), p.1021-1024

1984

Volltextzugriff (PDF)

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A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs

An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's

Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

An analytical method of evaluating variation of the threshold voltage shift caused by the negative-bias temperature stress in poly-Si TFTs

Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

Robotic crowd biology with Maholo LabDroids

Mechanism of negative-bias temperature instability in polycrystalline-silicon thin film transistors

A capacitorless twin-transistor random access memory (TTRAM) on SOI

Evaluation of surface defects on SIMOX and their influences on device characteristics

Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate

Impact of a vertical Φ-shape transistor (VΦT) cell for 1 Gbit DRAM and beyond

Investigation of anomalous leakage current in mesa-isolated SOI MOSFETs

Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si

Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits

A 400MHz 183mW microcontroller in body-tied SOI technology

Novel SOI wafer engineering using low stress and high mobility CMOSFET with -channel for embedded RF/analog applications

LPE crystal growth and magnetophonon resonance recombination of Hg1-xMnxTe

Cornerless active area cell and Bi-T-MOS process for sub-half micron SRAMs

Vertical Phi -shape transistor (V Phi T) cell for 1Gbit DRAM and beyond

Auger recombination oscillation of magnetoresistance in Hg1-xCdxTe under heated electron and hole condition

Magnetophonon resonance recombination of hot carriers with emission of two TA-phonons in LPE-HgTe

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