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A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

IEEE journal of solid-state circuits, 2007-04, Vol.42 (4), p.820-829

2007

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An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

IEEE transactions on electron devices, 2003-06, Vol.50 (6), p.1451-1458

2003

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Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

IEEE transactions on electron devices, 2001-09, Vol.48 (9), p.2065-2073

2001

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Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

IEEE transactions on electron devices, 2001-12, Vol.48 (12), p.2816-2822

2001

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Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 μm partially depleted SOI MOSFETs

IEEE transactions on electron devices, 2002-01, Vol.49 (1), p.55-60

2002

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Approaches to extra low voltage DRAM operation by SOI-DRAM

IEEE transactions on electron devices, 1998-05, Vol.45 (5), p.1000-1009

1998

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A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

IEEE journal of solid-state circuits, 1997-11, Vol.32 (11), p.1712-1720

1997

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Study of current induced magnetic domain wall movement with extremely low energy consumption by micromagnetic simulation

2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011, p.55-58

2011

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Impact of boron penetration from S/D-extension on gate-oxide reliability for 65-nm node CMOS and beyond

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, 2004, p.136-137

2004

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Suppression of charge carrier collection in diode with retrograde well and epitaxial layers for soft-error immunity

Nuclear instruments & methods in physics research. Section B, Beam interactions with materials and atoms, 1997-07, Vol.130 (1), p.524-527

1997

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Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2nm

Digest of technical papers - Symposium on VLSI Technology, 1996, p.210-211

1996

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New buried channel FLASH memory cell with symmetrical source/drain structure for 64Mbit or beyond

Digest of technical papers - Symposium on VLSI Technology, 1994, p.69-70

1994

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W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory

Japanese Journal of Applied Physics, 2004-04, Vol.43 (4S), p.1799

2004

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Highly reliable 0.15 mu m MOSFETs with surface proximity gettering (SPG) and nitrided oxide spacer using nitrogen implantation

Digest of technical papers - Symposium on VLSI Technology, 1995, p.19-20

1995

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Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2152

2005

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Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

IEEE transactions on electron devices, 1991-12, Vol.38 (12), p.2647-2656

1991

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Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2157

2005

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Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 [mu]m partially depleted SOI MOSFETs

IEEE transactions on electron devices, 2002-01, Vol.49 (1), p.55

2002

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Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25-micron partially depleted SOI MOSFETs

IEEE transactions on electron devices, 2002-01, Vol.49 (1), p.55-60

2002

Volltextzugriff (PDF)

Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 /spl mu/m partially depleted SOI MOSFETs

IEEE transactions on electron devices, 2002-01, Vol.49 (1), p.55-60

2002

Volltextzugriff (PDF)

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 mu m partially depleted SOIMOSFETs

IEEE transactions on electron devices, 2002-01, Vol.49 (1), p.55-60

2002

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Advanced Retrograde Well Technology for 90-nm-Node Embedded Static Random Access Memory Using High-Energy Parallel Beam

Japanese Journal of Applied Physics, 2002-04, Vol.41 (Part 1, No. 4B), p.2399-2403

2002

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Leakage Mechanism of Local Junctions Forming the Main or Tail Mode of Retention Characteristics for Dynamic Random Access Memories

Japanese Journal of Applied Physics, 2000-04, Vol.39 (4S), p.1963

2000

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Scaling guideline of DRAM memory cells for maintaining the retention time

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000, p.84-85

2000

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Submicrometer-gate MOSFET's by the use of focused-ion-beam exposure and a dry development technique

IEEE transactions on electron devices, 1987-02, Vol.34 (2), p.230-234

1987

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A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 μm partially depleted SOI MOSFETs

Approaches to extra low voltage DRAM operation by SOI-DRAM

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

Study of current induced magnetic domain wall movement with extremely low energy consumption by micromagnetic simulation

Impact of boron penetration from S/D-extension on gate-oxide reliability for 65-nm node CMOS and beyond

Suppression of charge carrier collection in diode with retrograde well and epitaxial layers for soft-error immunity

Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2nm

New buried channel FLASH memory cell with symmetrical source/drain structure for 64Mbit or beyond

W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory

Highly reliable 0.15 mu m MOSFETs with surface proximity gettering (SPG) and nitrided oxide spacer using nitrogen implantation

Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45 nm Node Devices and Beyond

Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 [mu]m partially depleted SOI MOSFETs

Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25-micron partially depleted SOI MOSFETs

Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 /spl mu/m partially depleted SOI MOSFETs

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 mu m partially depleted SOIMOSFETs

Advanced Retrograde Well Technology for 90-nm-Node Embedded Static Random Access Memory Using High-Energy Parallel Beam

Leakage Mechanism of Local Junctions Forming the Main or Tail Mode of Retention Characteristics for Dynamic Random Access Memories

Scaling guideline of DRAM memory cells for maintaining the retention time

Submicrometer-gate MOSFET's by the use of focused-ion-beam exposure and a dry development technique

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