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Optimization the ratio of concentrations of liquid organic and inorganic fertilizers to increase soybean production

IOP conference series. Earth and environmental science, 2021-07, Vol.800 (1), p.12029

2021

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Low-noise self-referenced CMOS oscillator

Electronics letters, 2009-08, Vol.45 (18), p.920-921

2009

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Cardiac resynchronization therapy: QRS index as a response predictor

CorSalud, 2019-07, Vol.11 (3), p.189-195

2019

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Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

IEEE journal of solid-state circuits, 2013-06, Vol.48 (6), p.1416-1428

2013

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Implantation of the cardioverter-defibrillator: Cuban Registry (2017)

CorSalud, 2018-07, Vol.10 (3), p.177-183

2018

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A 16-mW 78-dB SNDR 10-MHz BW CT \Delta \Sigma ADC Using Residue-Cancelling VCO-Based Quantizer

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.2916-2927

2012

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A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

IEEE journal of solid-state circuits, 2011-12, Vol.46 (12), p.3150-3162

2011

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A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

IEEE journal of solid-state circuits, 2011-08, Vol.46 (8), p.1870-1880

2011

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A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration

IEEE journal of solid-state circuits, 2011-12, Vol.46 (12), p.2759-2771

2011

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A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

IEEE journal of solid-state circuits, 2011-12, Vol.46 (12), p.3163-3173

2011

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Low-noise self-referenced CMOS oscillator

Electronics letters, 2009-08, Vol.45 (18), p.1-1

2009

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A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

2012 IEEE International Solid-State Circuits Conference, 2012, p.152-154

2012

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Digital clock and data recovery circuit design: Challenges and tradeoffs

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-8

2011

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Evolución clínica de pacientes con síndrome de Brugada y desfibriladores automáticos implantados. Experiencia en dos centros de atención terciaria

Revista cubana de cardiologia y cirugia cardiovascular, 2021-06, Vol.27 (2), p.e1106-e1106

2021

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Diferencias sexuales en el perfil clínico y terapéutico de pacientes con fibrilación auricular

CorSalud, 2021, Vol.13 (4), p.436-444

2021

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Terapia de resincronización cardíaca: Índice del QRS como predictor de respuesta

CorSalud, 2019, Vol.11 (3)

2019

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Implante del cardiodesfibrilador automático: Registro en Cuba (2017)

CorSalud, 2018, Vol.10 (3), p.177-183

2018

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A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

2011 IEEE International Solid-State Circuits Conference, 2011, p.92-94

2011

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Implante del cardiodesfibrilador automático: Registro en Cuba (2017)

CorSalud, 2018-09, p.177-183

2018

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A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS

2011 IEEE International Solid-State Circuits Conference, 2011, p.152-154

2011

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A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC

2012 IEEE International Solid-State Circuits Conference, 2012, p.242-244

2012

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A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

2011 IEEE International Solid-State Circuits Conference, 2011, p.438-450

2011

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Penggunaan Crude Antigen Cysticercus cellulosae Isolat Bali Untuk Optimalisasi Uji ELISA

Indonesia Medicus Veterinus, 2017-01, p.1-8

2017

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A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

2012 Symposium on VLSI Circuits (VLSIC), 2012, p.102-103

2012

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Optimization the ratio of concentrations of liquid organic and inorganic fertilizers to increase soybean production

Low-noise self-referenced CMOS oscillator

Cardiac resynchronization therapy: QRS index as a response predictor

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Implantation of the cardioverter-defibrillator: Cuban Registry (2017)

A 16-mW 78-dB SNDR 10-MHz BW CT \Delta \Sigma ADC Using Residue-Cancelling VCO-Based Quantizer

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

Low-noise self-referenced CMOS oscillator

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

Digital clock and data recovery circuit design: Challenges and tradeoffs

Evolución clínica de pacientes con síndrome de Brugada y desfibriladores automáticos implantados. Experiencia en dos centros de atención terciaria

Diferencias sexuales en el perfil clínico y terapéutico de pacientes con fibrilación auricular

Terapia de resincronización cardíaca: Índice del QRS como predictor de respuesta

Implante del cardiodesfibrilador automático: Registro en Cuba (2017)

A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration

Implante del cardiodesfibrilador automático: Registro en Cuba (2017)

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS

A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

Penggunaan Crude Antigen Cysticercus cellulosae Isolat Bali Untuk Optimalisasi Uji ELISA

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

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