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A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.124-133

2018

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256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.210-217

2017

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A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.204-212

2016

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An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.212-224

2021

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Prediction and Analysis of Radiated EMI From a Wafer-Level Package Based on IC Source Modeling

IEEE transactions on electromagnetic compatibility, 2024-02, Vol.66 (1), p.281-292

2024

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A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3307-3316

2024

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An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.121-131, Article 121

2008

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A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-3

2023

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PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1902-1905

2008

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Near-Field EMI Analysis of LPDDR5 DRAM at idle mode

2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI), 2023, p.311-314

2023

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7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM

2021 Symposium on VLSI Circuits, 2021, p.1-2

2021

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An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

2017 Symposium on VLSI Circuits, 2017, p.C194-C195

2017

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An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.492-617

2007

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25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.346-348

2021

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Automatic SPICE- Integrated Reinforcement Learning for Decap Optimization for EMI and Power Integrity

2022 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), 2022, p.565-569

2022

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11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.202-203

2017

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7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.130-131

2016

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Optimization of PDN decoupling capacitors for EMI Reduction based on Deep Reinforcement Learning

2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium, 2021, p.59-63

2021

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7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016, p.138-139

2016

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A Low EMI characteristic of LPDDR5 SDRAM with Edge-placed PADs and Short Re-Distribution Lines

2022 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), 2022, p.64-68

2022

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Characteristics and circuit model of a field emission triode

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 1998-03, Vol.16 (2), p.916-919

1998

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Characteristics and Circuit Model of a Field Emission Triode

10th International Conference on Vacuum Microelectronics, 1997, p.321-325

1997

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Osteomyelitis Caused by Hypervirulent Klebsiella pneumoniae : The First Korean Case With Family Spread

Annals of Laboratory Medicine, 2021, 41(2), , pp.250-254

2021

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A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

Prediction and Analysis of Radiated EMI From a Wafer-Level Package Based on IC Source Modeling

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

Near-Field EMI Analysis of LPDDR5 DRAM at idle mode

7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM

A 1.2V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package employing F-chip for low power and high performance storage applications

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

Automatic SPICE- Integrated Reinforcement Learning for Decap Optimization for EMI and Power Integrity

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers

Optimization of PDN decoupling capacitors for EMI Reduction based on Deep Reinforcement Learning

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

A Low EMI characteristic of LPDDR5 SDRAM with Edge-placed PADs and Short Re-Distribution Lines

Characteristics and circuit model of a field emission triode

Characteristics and Circuit Model of a Field Emission Triode

Osteomyelitis Caused by Hypervirulent Klebsiella pneumoniae : The First Korean Case With Family Spread

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