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MAC protocol based on cross-layer design methodology for fast link in wireless communication systems

IEICE Electronics Express, 2007-01, Vol.4 (19), p.593-599

2007

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Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

IEEE journal of solid-state circuits, 2002-01, Vol.37 (1), p.38-50

2002

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PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

IEEE journal of solid-state circuits, 2004-05, Vol.39 (5), p.740-750

2004

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A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI

IEEE journal of solid-state circuits, 2000-12, Vol.35 (12), p.1988-1991

2000

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A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2002-04, Vol.49 (4), p.266-272

2002

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A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

IEEE journal of solid-state circuits, 1999-06, Vol.34 (6), p.805-812

1999

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20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems

IEEE journal of solid-state circuits, 1993-02, Vol.28 (2), p.115-122

Ichino, H.

1993

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A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic

IEEE journal of solid-state circuits, 1997-02, Vol.32 (2), p.215-221

1997

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Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks

IEICE transactions on communications, 2005-10, Vol.E88-B (10), p.3952-3961

TERADA, K.

2005

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An ultracompact, 2-cc-size, low-power 2.5-Gb/s optical receiver module incorporating an MU receptacle

Journal of lightwave technology, 1999-11, Vol.17 (11), p.2349-2355

1999

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ENHANCED NETWORK SIGNALING FOR 10 GIGABIT ETHERNET TO ACHIEVE A LAN-WAN SEAMLESS INTERFACE AND ITS IMPLEMENTATION IN THE PHY-LSI/TRANSCEIVER MODULE

International journal of high speed electronics, 2005-09, Vol.15 (3), p.667-704

2005

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A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design

IEEE journal of solid-state circuits, 1999-01, Vol.34 (1), p.12-17

1999

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Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops

IEEE journal of solid-state circuits, 1995-01, Vol.30 (1), p.19-24

1995

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High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing

IEEE journal of solid-state circuits, 1998-10, Vol.33 (10), p.1536-1544

1998

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Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit

IEEE journal of solid-state circuits, 1994-07, Vol.29 (7), p.754-760

1994

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Over-10-Gb/s IC's for future lightwave communications

Journal of lightwave technology, 1994-02, Vol.12 (2), p.308-319

1994

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2.5 Gb/s 557 mW STM-16 regenerator section terminating LSI chip

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, Vol.40, p.158-159

1997

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18-GHz 1/8 dynamic frequency divider using Si bipolar technologies

IEEE journal of solid-state circuits, 1989-12, Vol.24 (6), p.1723-1728

1989

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High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

IEEE journal of solid-state circuits, 1994-05, Vol.29 (5), p.546-550

1994

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12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology

IEEE journal of solid-state circuits, 1990-12, Vol.25 (6), p.1538-1543

1990

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A bipolar monolithic multigigabit/s decision circuit

IEEE journal of solid-state circuits, 1984-08, Vol.19 (4), p.462-467

1984

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Design and application of a 2500-gate bipolar macrocell array

IEEE journal of solid-state circuits, 1985-10, Vol.20 (5), p.1025-1031

1985

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A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit

2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000, Vol.5, p.261-264 vol.5

2000

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A 10 Gb/s decision circuit using AlGaAs/GaAs HBT technology

1990 37th IEEE International Conference on Solid-State Circuits, 1990, p.188-189

1990

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A compact MU interface 2.5-Gb/s optical transmitter module with an embedded LD-driver IC

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206), 1998, p.184-191

1998

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MAC protocol based on cross-layer design methodology for fast link in wireless communication systems

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI

A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic

Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks

An ultracompact, 2-cc-size, low-power 2.5-Gb/s optical receiver module incorporating an MU receptacle

ENHANCED NETWORK SIGNALING FOR 10 GIGABIT ETHERNET TO ACHIEVE A LAN-WAN SEAMLESS INTERFACE AND ITS IMPLEMENTATION IN THE PHY-LSI/TRANSCEIVER MODULE

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing

Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit

Over-10-Gb/s IC's for future lightwave communications

2.5 Gb/s 557 mW STM-16 regenerator section terminating LSI chip

18-GHz 1/8 dynamic frequency divider using Si bipolar technologies

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology

A bipolar monolithic multigigabit/s decision circuit

Design and application of a 2500-gate bipolar macrocell array

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit

A 10 Gb/s decision circuit using AlGaAs/GaAs HBT technology

A compact MU interface 2.5-Gb/s optical transmitter module with an embedded LD-driver IC

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