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Histogram-Based Calibration Method for Pipeline ADCs

PloS one, 2015-06, Vol.10 (6), p.e0129736-e0129736

2015

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Multi-operation-based Constrained Random Verification for On-Chip Memory

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(3), 63, pp.423-426

2015

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A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving - 46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal

IEEE journal of solid-state circuits, 2024-08, p.1-14

2024

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A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process

IEEE journal of solid-state circuits, 2023-12, Vol.58 (12), p.3408-3420

2023

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A low-cost DDEM ADC structure for the testing of high-performance DACs

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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A new static test of a DAC with a built-in structure

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach

IEICE transactions on electronics, 2011, Vol.E94-C (8), p.1344-1347

2011

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A 50-Gb/s Compact RadCom E-Band Transmitter With Phase-Controlled Push-Push Quadrupler and Stacked-FET Power Amplifier

IEEE solid-state circuits letters, 2021, Vol.4, p.150-153

2021

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4.2 A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.78-80

2024

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A New Analog-to-Digital Converter BIST Considering a Transient Zone

IEICE transactions on electronics, 2007-11, Vol.E90-C (11), p.2161-2163

2007

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A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters

IEICE transactions on electronics, 2008, Vol.E91-C (4), p.670-672

2008

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31.2 A Fully Integrated IEEE 802.15.4/4z-Compliant 6.5-to-8GHz UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28nm Process

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.462-464

2023

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Reduced-code test method using sub-histograms for pipelined ADCs

IEICE Electronics Express, 2015, Vol.12 (12), p.20150417-20150417

2015

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Multi-operation-based Constrained Random Verification for On-Chip Memory

Journal of semiconductor technology and science, 2015, Vol.15 (3), p.423-426

2015

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Simultaneous Static Testing of A/D and D/A Converters Using a Built-in Structure

ETRI journal, 2013, Vol.35 (1), p.109-119

2013

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Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

ETRI Journal, 2013, 35(1), , pp.109-119

2013

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Simultaneous Static Testing of A/D and D/A Converters Using a Built-in Structure

ETRI journal, 2013-02, Vol.35 (1), p.0-0

2013

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A new scan slice encoding scheme with flexible code for test data compression

2010 International SoC Design Conference, 2010, p.217-220

2010

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A BIST architecture for multiple DACs in an LTPS TFT-LCD source driver IC

2009 International SoC Design Conference (ISOCC), 2009, p.120-123

2009

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Variable-length block nine-coded compression technique with Huffman codes and symbol merging

2008 International SoC Design Conference, 2008, Vol.1, p.I-210-I-213

2008

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Advanced process design of subcooling re-liquefaction system considering storage pressure for a liquefied CO2 carrier

Energy (Oxford), 2024-04, Vol.293, p.130556, Article 130556

2024

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Automated Information Extraction from Thyroid Operation Narrative: A Comparative Study of GPT-4 and Fine-tuned KoELECTRA

AMIA Summits on Translational Science proceedings, 2024, Vol.2024, p.249-257

2024

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Histogram-Based Calibration Method for Pipeline ADCs

Multi-operation-based Constrained Random Verification for On-Chip Memory

A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving - 46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal

A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process

A low-cost DDEM ADC structure for the testing of high-performance DACs

A new static test of a DAC with a built-in structure

Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach

A 50-Gb/s Compact RadCom E-Band Transmitter With Phase-Controlled Push-Push Quadrupler and Stacked-FET Power Amplifier

4.2 A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46dB TX/RX EVM Floor at 7.1GHz for a 4K-QAM 320MHz Signal

A New Analog-to-Digital Converter BIST Considering a Transient Zone

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters

31.2 A Fully Integrated IEEE 802.15.4/4z-Compliant 6.5-to-8GHz UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28nm Process

Reduced-code test method using sub-histograms for pipelined ADCs

Multi-operation-based Constrained Random Verification for On-Chip Memory

Simultaneous Static Testing of A/D and D/A Converters Using a Built-in Structure

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Simultaneous Static Testing of A/D and D/A Converters Using a Built-in Structure

A new scan slice encoding scheme with flexible code for test data compression

A BIST architecture for multiple DACs in an LTPS TFT-LCD source driver IC

Variable-length block nine-coded compression technique with Huffman codes and symbol merging

Advanced process design of subcooling re-liquefaction system considering storage pressure for a liquefied CO2 carrier

Automated Information Extraction from Thyroid Operation Narrative: A Comparative Study of GPT-4 and Fine-tuned KoELECTRA

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