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Accelerating advanced MRI reconstructions on GPUs

Journal of parallel and distributed computing, 2008-10, Vol.68 (10), p.1307-1318

2008

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An architectural framework for runtime optimization

IEEE transactions on computers, 2001-06, Vol.50 (6), p.567-589, Article 567

2001

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Program decision logic optimization using predication and control speculation

Proceedings of the IEEE, 2001, Vol.89 (11), p.1660-1675

2001

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A power controlled multiple access protocol for wireless packet networks

Proceedings IEEE INFOCOM 2001. Conference on Computer Communications. Twentieth Annual Joint Conference of the IEEE Computer and Communications Society (Cat. No.01CH37213), 2001, Vol.1, p.219-228 vol.1

2001

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Run-time cache bypassing

IEEE transactions on computers, 1999-12, Vol.48 (12), p.1338-1354

1999

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A study of the effects of compiler-controlled speculation on instruction and data caches

Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences, 1995, Vol.1, p.211-220 vol.1

1995

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FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

2009 IEEE 7th Symposium on Application Specific Processors, 2009, p.35-42

2009

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Accelerating MR image reconstruction on GPUs

2009 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2009, p.1283-1286

2009

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Combining trace sampling with single pass methods for efficient cache simulation

IEEE transactions on computers, 1998-06, Vol.47 (6), p.714-720

1998

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Enhancing loop buffering of media and telecommunications applications using low-overhead predication

Proceedings of the annual International Symposium on Microarchitecture, 2001, p.262-273

2001

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Modulo schedule buffers

Proceedings of the annual International Symposium on Microarchitecture, 2001, p.138-149

2001

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Many-core parallel computing - Can compilers and tools do the heavy lifting?

2009 IEEE International Symposium on Parallel & Distributed Processing, 2009, p.1-1

Hwu, W.-m.W.

2009

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The application of compiler-assisted multiple-instruction retry to VLIW architectures

Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, 1994, p.51-58

1994

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Code reordering and speculation support for dynamic optimization systems

Proceedings of the Conference on Parallel Architectures and Compilation Techniques, 2001

2001

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Long time-scale simulations of in vivo diffusion using GPU hardware

2009 IEEE International Symposium on Parallel & Distributed Processing, 2009, p.1-8

2009

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The susceptibility of programs to context switching

IEEE transactions on computers, 1994-09, Vol.43 (9), p.994-1003

1994

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The importance of prepass code scheduling for superscalar and superpipelined processors

IEEE transactions on computers, 1995-03, Vol.44 (3), p.353-370

1995

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Benchmark characterization

Computer (Long Beach, Calif.), 1991-01, Vol.24 (1), p.48-56

1991

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Field-testing IMPACT EPIC research results in Itanium 2

Proceedings. 31st Annual International Symposium on Computer Architecture, 2004, 2004, p.26-37

2004

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Compilers for improved Java performance

Computer (Long Beach, Calif.), 1997-06, Vol.30 (6), p.67-75

1997

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Compiler-based multiple instruction retry

IEEE transactions on computers, 1995-01, Vol.44 (1), p.35-46

1995

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The parallelization of video processing

IEEE signal processing magazine, 2009-11, Vol.26 (6), p.103-112

2009

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Compiler-assisted multiple instruction rollback recovery using a read buffer

IEEE transactions on computers, 1995-09, Vol.44 (9), p.1096-1107

1995

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A hardware mechanism for dynamic extraction and relayout of program hot spots

International Symposium on Computer Architecture: Proceedings of the 27th annual international symposium on Computer architecture : Vancouver, British Columbia, Canada, 2000, p.59-70

2000

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