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Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

IEEE transactions on very large scale integration (VLSI) systems, 2017-11, Vol.25 (11), p.3033-3044

2017

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Fixed-Complexity Tree Search Schemes for Detecting Generalized Spatially Modulated Signals: Algorithms and Hardware Architectures

IEEE transactions on circuits and systems. I, Regular papers, 2021-02, Vol.68 (2), p.904-917

2021

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Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.361-366

2012

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A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video

IEEE transactions on circuits and systems for video technology, 2015-04, Vol.25 (4), p.674-687

2015

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A Low-Complexity Maximum Likelihood Detector for the Spatially Modulated Signals: Algorithm and Hardware Implementation

IEEE transactions on circuits and systems. II, Express briefs, 2019-11, Vol.66 (11), p.1820-1824

2019

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Single-ended structure sense-amplifier-based flip-flop for low-power systems

Electronics letters, 2015-01, Vol.51 (1), p.20-21

2015

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A Constant Throughput Geometric Mean Decomposition Scheme Design for Wireless MIMO Precoding

IEEE transactions on vehicular technology, 2013-06, Vol.62 (5), p.2080-2090

2013

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An Efficient Lossless Compression Scheme for Hyperspectral Images Using Two-Stage Prediction

IEEE geoscience and remote sensing letters, 2010-07, Vol.7 (3), p.558-562

2010

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A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2007-05, Vol.54 (5), p.1050-1059

2007

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A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation

IEEE transactions on circuits and systems. I, Regular papers, 2014-04, Vol.61 (4), p.1170-1182

2014

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Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

IEEE transactions on very large scale integration (VLSI) systems, 2012-09, Vol.20 (9), p.1738-1742

2012

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VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems

IEEE access, 2019, Vol.7, p.85925-85936

2019

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Design and Chip Implementation of A SMI/MVDR Dual-mode Beamformer for Wireless MIMO Communication Systems

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign

IEEE embedded systems letters, 2011-03, Vol.3 (1), p.20-23

2011

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Sensor Data Fusion of Intelligent Autonomous Mover for Object Detection and Collision Avoidance in Environments with Surrounding Crowds

2021 IEEE International Conference on Consumer Electronics (ICCE), 2021, p.1-4

2021

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Efficient Image Aided Odometry Estimation Scheme for LiDAR Camera based SLAM Systems

2023 IEEE 12th Global Conference on Consumer Electronics (GCCE), 2023, p.115-116

2023

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High-speed, low-complexity systolic designs of novel iterative division algorithms in GF(2/sup m/)

IEEE transactions on computers, 2004-03, Vol.53 (3), p.375-380

2004

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A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Electronics (Basel), 2020-04, Vol.9 (4), p.641

2020

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Low power 10-transistor full adder design based on degenerate pass transistor logic

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.496-499

2012

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A low complexity complex QR factorization design for signal detection in MIMO OFDM systems

2008 IEEE International Symposium on Circuits and Systems, 2008, p.932-935

2008

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A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2010, Vol.E93-A (4), p.843-845

2010

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Low Power Pulse Generator Design Using Hybrid Logic

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2010, Vol.E93-A (6), p.1266-1268

2010

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Implementations of Signal-Processing Algorithms for OFDM Systems

Journal of Electrical and Computer Engineering, 2012-01, Vol.2012 (2012), p.902-903

2012

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Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement

Journal of signal processing systems, 2015-01, Vol.78 (1), p.1-3

2015

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Low complexity baseband transceiver design for narrow band power line communication

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.442-445

2011

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Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

Fixed-Complexity Tree Search Schemes for Detecting Generalized Spatially Modulated Signals: Algorithms and Hardware Architectures

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video

A Low-Complexity Maximum Likelihood Detector for the Spatially Modulated Signals: Algorithm and Hardware Implementation

Single-ended structure sense-amplifier-based flip-flop for low-power systems

A Constant Throughput Geometric Mean Decomposition Scheme Design for Wireless MIMO Precoding

An Efficient Lossless Compression Scheme for Hyperspectral Images Using Two-Stage Prediction

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems

Design and Chip Implementation of A SMI/MVDR Dual-mode Beamformer for Wireless MIMO Communication Systems

Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign

Sensor Data Fusion of Intelligent Autonomous Mover for Object Detection and Collision Avoidance in Environments with Surrounding Crowds

Efficient Image Aided Odometry Estimation Scheme for LiDAR Camera based SLAM Systems

High-speed, low-complexity systolic designs of novel iterative division algorithms in GF(2/sup m/)

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Low power 10-transistor full adder design based on degenerate pass transistor logic

A low complexity complex QR factorization design for signal detection in MIMO OFDM systems

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits

Low Power Pulse Generator Design Using Hybrid Logic

Implementations of Signal-Processing Algorithms for OFDM Systems

Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement

Low complexity baseband transceiver design for narrow band power line communication

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