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Ring-opening polymerization-induced crystallization-driven self-assembly of poly-L-lactide-block-polyethylene glycol block copolymers (ROPI-CDSA)

Nature communications, 2020-09, Vol.11 (1), p.4690-12, Article 4690

2020

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Direct Observation of Amorphous Precursor Phases in the Nucleation of Protein–Metal–Organic Frameworks

Journal of the American Chemical Society, 2020-01, Vol.142 (3), p.1433-1442

2020

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Ultrahigh Molecular Weight Hydrophobic Acrylic and Styrenic Polymers through Organic-Phase Photoiniferter-Mediated Polymerization

ACS macro letters, 2020-04, Vol.9 (4), p.613-618

2020

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Waste-Free Fully Electrically Fueled Dissipative Self-Assembly System

Journal of the American Chemical Society, 2023-02, Vol.145 (6), p.3727-3735

2023

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Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA

IEEE journal of solid-state circuits, 2009-10, Vol.44 (10), p.2780-2789

2009

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Facile Synthesis of Multifunctional Bioreducible Polymers for mRNA Delivery

Chemistry : a European journal, 2023-02, Vol.29 (12), p.e202203393-n/a

2023

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A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2022-02, Vol.69 (2), p.620-633

2022

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Nonionic Block Copolymer Coacervates

Macromolecules, 2020-07, Vol.53 (14), p.6078-6086

2020

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3D Visualization of Proteins within Metal–Organic Frameworks via Ferritin‐Enabled Electron Microscopy

Advanced functional materials, 2024-03, Vol.34 (13)

2024

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Digital Background Calibration of a Split Current-Steering DAC

IEEE transactions on circuits and systems. I, Regular papers, 2019-08, Vol.66 (8), p.2854-2864

2019

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A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors

IEEE journal of solid-state circuits, 2010-10, Vol.45 (10), p.2091-2103

2010

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The role of protein folding in prenucleation clusters on the activity of enzyme@metal–organic frameworks

Journal of materials chemistry. A, Materials for energy and sustainability, 2024-01, Vol.12 (2), p.813-823

2024

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A Two-Step ADC With Statistical Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2020-08, Vol.67 (8), p.2588-2601

2020

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Ring-Opening Polymerization of Cyclic Esters and Carbonates with (Thio)urea/Cyclopropenimine Organocatalytic Systems

ACS macro letters, 2024-01, Vol.13 (2), p.181-188

2024

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Iterative Gain Enhancement in an Algorithmic ADC

IEEE transactions on circuits and systems. I, Regular papers, 2016-04, Vol.63 (4), p.459-469

2016

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A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

IEEE journal of solid-state circuits, 2005-05, Vol.40 (5), p.1038-1046

2005

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A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

IEEE journal of solid-state circuits, 2004-11, Vol.39 (11), p.1799-1808

2004

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A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters

IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.240-246

2009

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Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling

IEEE journal of solid-state circuits, 2013-03, Vol.48 (3), p.749-759

2013

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A Pipelined ADC With Metastability Error Rate 10 ^$ Errors/Sample

IEEE journal of solid-state circuits, 2012-09, Vol.47 (9), p.2119-2128

2012

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An Integrator-Based Pipelined ADC With Digital Calibration

IEEE transactions on circuits and systems. II, Express briefs, 2015-09, Vol.62 (9), p.831-835

2015

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Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors

IEEE journal of solid-state circuits, 2014-06, Vol.49 (6), p.1397-1407

2014

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A Digitally Corrected 5-mW 2-MS/s SC ΔΣ ADC in 0.25-μm CMOS With 94-dB SFDR

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2673-2684

2011

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Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer

IEEE transactions on circuits and systems. I, Regular papers, 2012-03, Vol.59 (3), p.652-663

2012

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A digital background calibration technique for time-interleaved analog-to-digital converters

IEEE journal of solid-state circuits, 1998-12, Vol.33 (12), p.1904-1911

1998

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Ring-opening polymerization-induced crystallization-driven self-assembly of poly-L-lactide-block-polyethylene glycol block copolymers (ROPI-CDSA)

Direct Observation of Amorphous Precursor Phases in the Nucleation of Protein–Metal–Organic Frameworks

Ultrahigh Molecular Weight Hydrophobic Acrylic and Styrenic Polymers through Organic-Phase Photoiniferter-Mediated Polymerization

Waste-Free Fully Electrically Fueled Dissipative Self-Assembly System

Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA

Facile Synthesis of Multifunctional Bioreducible Polymers for mRNA Delivery

A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration

Nonionic Block Copolymer Coacervates

3D Visualization of Proteins within Metal–Organic Frameworks via Ferritin‐Enabled Electron Microscopy

Digital Background Calibration of a Split Current-Steering DAC

A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors

The role of protein folding in prenucleation clusters on the activity of enzyme@metal–organic frameworks

A Two-Step ADC With Statistical Calibration

Ring-Opening Polymerization of Cyclic Esters and Carbonates with (Thio)urea/Cyclopropenimine Organocatalytic Systems

Iterative Gain Enhancement in an Algorithmic ADC

A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters

Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling

A Pipelined ADC With Metastability Error Rate 10 ^$ Errors/Sample

An Integrator-Based Pipelined ADC With Digital Calibration

Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors

A Digitally Corrected 5-mW 2-MS/s SC ΔΣ ADC in 0.25-μm CMOS With 94-dB SFDR

Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer

A digital background calibration technique for time-interleaved analog-to-digital converters

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