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Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2023, p.1-7

2023

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Transparent In-Circuit Assertions for FPGAs

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-07, Vol.36 (7), p.1193-1202

2017

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RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration

ACM transactions on reconfigurable technology and systems, 2023-09, Vol.16 (4), p.1-30, Article 59

2023

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Accelerating SpMV on FPGAs by Compressing Nonzero Values

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 2015, p.64-67

2015

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100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs

Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022, p.1-16

2022

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Scalable Signal Selection for Post-Silicon Debug

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1103-1115

2013

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Incremental Trace-Buffer Insertion for FPGA Debug

IEEE transactions on very large scale integration (VLSI) systems, 2014-04, Vol.22 (4), p.850-863

2014

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Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-6

2023

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Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

ACM transactions on design automation of electronic systems, 2014-03, Vol.19 (2), p.1-23

2014

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KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs

ACM transactions on reconfigurable technology and systems, 2018-03, Vol.11 (1), p.1-22

2018

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Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding

IEEE transactions on very large scale integration (VLSI) systems, 2012-03, Vol.20 (3), p.437-448

2012

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KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs

2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016, p.56-63

2016

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Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry

2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, p.1-4

Hung, Eddie

2015

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DynaRapid: Fast-Tracking from C to Routed Circuits

2024 34th International Conference on Field-Programmable Logic and Applications (FPL), 2024, p.24-32

2024

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A configurable and programmable motion estimation processor for the H.264 video codec

2008 International Conference on Field Programmable Logic and Applications, 2008, p.149-154

2008

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Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, 2013, p.19-28

2013

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Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019, p.1-4

2019

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Transparent insertion of latency-oblivious logic onto FPGAs

2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014, p.1-8

2014

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EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019, p.5-8

2019

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Extending post-silicon coverage measurement using time-multiplexed FPGA overlays

2018 IEEE 23rd European Test Symposium (ETS), 2018, p.1-2

2018

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Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, 2013, p.45-52

2013

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KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications

Proceedings of the International Workshop on OpenCL, 2018, p.1-1

2018

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STRIPE: Signal selection for runtime power estimation

2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017, p.1-8

2017

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Limitations of incremental signal-tracing for FPGA debug

22nd International Conference on Field Programmable Logic and Applications (FPL), 2012, p.49-56

2012

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Speculative Debug Insertion for FPGAs

2011 21st International Conference on Field Programmable Logic and Applications, 2011, p.524-531

2011

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Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling

Transparent In-Circuit Assertions for FPGAs

RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration

Accelerating SpMV on FPGAs by Compressing Nonzero Values

100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs

Scalable Signal Selection for Post-Silicon Debug

Incremental Trace-Buffer Insertion for FPGA Debug

Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry

Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network

KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs

Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding

KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs

Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry

DynaRapid: Fast-Tracking from C to Routed Circuits

A configurable and programmable motion estimation processor for the H.264 video codec

Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers

Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs

Transparent insertion of latency-oblivious logic onto FPGAs

EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation

Extending post-silicon coverage measurement using time-multiplexed FPGA overlays

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices

KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications

STRIPE: Signal selection for runtime power estimation

Limitations of incremental signal-tracing for FPGA debug

Speculative Debug Insertion for FPGAs

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